公开(公告)号：US20230387216A1

公开(公告)日：2023-11-30

申请号：US18363214

申请日：2023-08-01

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tatsuo SHIMIZU ,  Yukio NAKABAYASHI ,  Johji NISHIO ,  Chiharu OTA ,  Toshihide ITO

IPC: H01L29/16 ,  C23C16/453 ,  H01L29/20

CPC classification number: H01L29/1608 ,  H01L29/517 ,  H01L29/2003 ,  C23C16/453

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm−3. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm−3, and a carbon concentration at the position is equal to or less than 1×1018 cm−3.

公开(公告)号：US20220416030A1

公开(公告)日：2022-12-29

申请号：US17902074

申请日：2022-09-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tatsuo SHIMIZU ,  Yukio NAKABAYASHI ,  Johji NISHIO ,  Chiharu OTA ,  Toshihide ITO

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  B66B11/04 ,  B60K1/00 ,  B61C17/00 ,  H02P27/06 ,  B61C3/00 ,  B60L53/20

Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm−3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm−3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm−3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm−3.

公开(公告)号：US20200176571A1

公开(公告)日：2020-06-04

申请号：US16782826

申请日：2020-02-05

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tatsuo SHIMIZU ,  Johji NISHIO ,  Takashi SHINOHE

IPC: H01L29/16 ,  H01L29/04 ,  H01L29/167 ,  H01L29/49 ,  H01L21/04 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

Abstract: A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3C—SiC.

公开(公告)号：US20190245042A1

公开(公告)日：2019-08-08

申请号：US16055286

申请日：2018-08-06

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Johji NISHIO ,  Tatsuo Shimizu ,  Mitsuhiro Kushibe

IPC: H01L29/16 ,  H01L21/02

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region including first and second compounds including silicon and carbon. The first semiconductor region includes first to third regions contacting the second semiconductor region. The third region is positioned between the first and second regions. The first and second regions include a first element. The first element includes at least one selected from the group consisting of second and third elements. The second element includes at least one selected from the group consisting of Ar, Kr, Xe, and Rn. The third element includes at least one selected from the group consisting of Cl, Br, I, and At. The third region does not include the first element, or a concentration of the first element in the third region is lower than concentrations of the first element in the first and second regions.

公开(公告)号：US20140252378A1

公开(公告)日：2014-09-11

申请号：US14199018

申请日：2014-03-06

Applicant: Kabushiki Kaisha Toshiba

Inventor： Chiharu OTA ,  Johji NISHIO ,  Takashi SHINOHE

IPC: H01L29/16 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02609 ,  H01L29/045 ,  H01L29/32 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/861

Abstract: According to one embodiment, a semiconductor substrate includes a substrate and a semiconductor layer. The substrate has a first surface and containing a silicon carbide. The semiconductor layer is provided on the first surface. The semiconductor layer has a thickness of H centimeters in a perpendicular direction to the first surface. The semiconductor layer contains an epitaxially grown silicon carbide with an off angle θ provided relative to a (0001) face of the substrate. The semiconductor layer includes k pieces of basal plane dislocation per one square centimeter viewed in the perpendicular direction. When S=(½)×H2/(tan θ(sin θ×tan 30°)) square centimeters, k×S

Abstract translation: 根据一个实施例，半导体衬底包括衬底和半导体层。 衬底具有第一表面并且包含碳化硅。 半导体层设置在第一表面上。 半导体层在与第一表面垂直的方向上具有H厘米的厚度。 半导体层包含具有偏角的外延生长的碳化硅; 相对于衬底的（0001）面提供。 半导体层包括在垂直方向上观察的每平方厘米k个基面位错。 当S =（1/2）×H2 /（tan＆thetas;（sin＆thetas;×tan 30°））平方厘米时，满足k×S <0.075平方厘米。

公开(公告)号：US20150034974A1

公开(公告)日：2015-02-05

申请号：US14448345

申请日：2014-07-31

Applicant: Kabushiki Kaisha Toshiba

Inventor： Johji NISHIO ,  Tatsuo SHIMIZU ,  Ryosuke IIJIMA ,  Chiharu OTA ,  Takashi SHINOHE

IPC: H01L29/36 ,  H01L29/167 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/36 ,  H01L21/046 ,  H01L29/1029 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802

Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer on the first SiC epitaxial layer containing a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the element A being higher than 0.33 but lower than 1.0; a surface region at the surface of the second SiC epitaxial layer containing the element A at a lower concentration than in the second SiC epitaxial layer, the ratio being higher than in the second SiC epitaxial layer; n-type first and second SiC regions; a gate insulating film; a gate electrode; a first electrode; and a second electrode.

Abstract translation: 实施例的半导体器件包括：n型第一SiC外延层; 在包含p型杂质和n型杂质的第一SiC外延层上的p型第二SiC外延层，p型杂质为元素A，n型杂质为元素D，元素A 并且形成Al，Ga或In和N的组合的元素D和/或B和P的组合，元素D与元素A的浓度比率高于0.33但低于1.0; 所述第二SiC外延层的表面的表面区域含有比所述第二SiC外延层低的浓度的所述元素A，所述比率高于所述第二SiC外延层中的比率; n型第一和第二SiC区域; 栅极绝缘膜; 栅电极; 第一电极; 和第二电极。

公开(公告)号：US20150034973A1

公开(公告)日：2015-02-05

申请号：US14448287

申请日：2014-07-31

Applicant: Kabushiki Kaisha Toshiba

Inventor： Johji NISHIO ,  Tatsuo SHIMIZU ,  Chiharu OTA ,  Takashi SHINOHE

IPC: H01L29/167 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/167 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66477 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7802

Abstract: A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer provided on the first SiC epitaxial layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 1.0; n-type first and second SiC regions provided in the surface of the second SiC epitaxial layer; a gate insulating film; a gate electrode; a first electrode provided on the second SiC region; and a second electrode provided on the opposite side from the first electrode.

Abstract translation: 实施例的半导体器件包括：n型第一SiC外延层; 设置在第一SiC外延层上并包含p型杂质和n型杂质的p型第二SiC外延层，p型杂质为元素A，n型杂质为元素D， 元素A和形成Al，Ga或In和N的组合的元素D和/或B和P的组合，元素D的浓度与组合中的元素A的浓度之比（s ）高于0.33但低于1.0; 设置在第二SiC外延层表面的n型第一和第二SiC区域; 栅极绝缘膜; 栅电极; 设置在所述第二SiC区域上的第一电极; 以及设置在与第一电极相对的一侧的第二电极。

公开(公告)号：US20140335682A1

公开(公告)日：2014-11-13

申请号：US14339165

申请日：2014-07-23

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Chiharu OTA ,  Takashi SHINOHE ,  Makoto MIZUKAMI ,  Johji NISHIO

IPC: H01L29/16 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L29/47

CPC classification number: H01L29/1608 ,  H01L21/02529 ,  H01L21/26513 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer. The semiconductor device also includes a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode while being in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substrate.

Abstract translation: 根据实施例的半导体器件包括第一导电型半导体衬底; 形成在半导体衬底上的第一导电型第一半导体层，其杂质浓度低于半导体衬底的杂质浓度; 外延形成在第一半导体层上的第二导电型第二半导体层; 以及外延形成在所述第二半导体层上，并且具有比所述第二半导体层的杂质浓度高的杂质浓度的第二导电型第三半导体层。 半导体器件还包括形成在第三半导体层中的凹部，并且至少侧面和底面的角部位于第二半导体层中。 半导体器件还包括与第三半导体层接触的第一电极; 第二电极，其与所述第一电极连接，同时在所述凹部的底表面处与所述第二半导体层接触; 以及与半导体衬底的下表面接触的第三电极。

公开(公告)号：US20140284619A1

公开(公告)日：2014-09-25

申请号：US14205792

申请日：2014-03-12

Applicant: Kabushiki Kaisha Toshiba

Inventor： Johji NISHIO ,  Tatsuo Shimizu ,  Chiharu Ota ,  Takashi Shinohe

IPC: H01L29/16

CPC classification number: H01L29/1608 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/045 ,  H01L29/66068 ,  H01L29/7827

Abstract: An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.

Abstract translation: 实施方案的SiC外延晶片包括SiC衬底和形成在SiC衬底上并包含p型杂质和n型杂质的p型第一SiC外延层。 元素A和元素D是Al（铝），Ga（镓）或In（铟）和N（氮）的组合，和/或B（硼）和P（磷）的组合，当p 型杂质是元素A，n型杂质是元素D.组合（D）中元素D的浓度与元素A的浓度之比高于0.33但低于1.0。

公开(公告)号：US20140209927A1

公开(公告)日：2014-07-31

申请号：US14167295

申请日：2014-01-29

Applicant: Kabushiki Kaisha Toshiba

Inventor： Johji NISHIO ,  Tatsuo SHIMIZU ,  Chiharu OTA ,  Takashi SHINOHE

IPC: H01L29/16 ,  H01L21/265

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L29/161 ,  H01L29/34 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/8613

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.

Abstract translation: 根据一个实施例，半导体器件包括由碳化硅制成的第一导电类型的第一半导体层; 以及由碳化硅制成的第二导电类型的第二半导体层，放置在与第一半导体层的结合处，并且包含电非活性元件。