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    Image reading device, recording medium storing image reading program, image reading method and data signal
    1.
    发明申请
    Image reading device, recording medium storing image reading program, image reading method and data signal 审中-公开
    图像读取装置，存储图像读取程序的记录介质，图像读取方法和数据信号

    公开(公告)号：US20090097079A1

    公开(公告)日：2009-04-16

    申请号：US12081816

    申请日：2008-04-22

    Applicant: Hidetaka Hama ,  Kouji Yorimoto ,  Junichi Goto ,  Kenji Nomura ,  Kazuhiko Minowa

    Inventor： Hidetaka Hama ,  Kouji Yorimoto ,  Junichi Goto ,  Kenji Nomura ,  Kazuhiko Minowa

    IPC: H04N1/04

    CPC classification number: H04N1/00795 ,  H04N1/00816 ,  H04N1/1013 ,  H04N1/193 ,  H04N2201/0081

    Abstract: An image reading device, which includes: an original document reading section that emits light to an original document and in the vicinity of the original document, receives reflected light and outputs image signals; an original document positioning guide that has at least a first color and a second color on a side receiving the light emitted from the original document reading section, and is used for settling a position of the original document; a detection section that monitors a first image signal in a scanning direction from the first color to the original document and a second image signal in a scanning direction from the second color to the original document, and detects a position for extracting image signals corresponding to the light reflected on the original document on the basis of a change occurring in either of the first image signal or the second image signal.

    Abstract translation: 一种图像读取装置，包括：原稿读取部，其对原稿发光，并在原稿附近，接收反射光并输出图像信号; 原稿定位引导件，其在接收从原始文档读取部分发射的光的一侧具有至少第一颜色和第二颜色，并且用于确定原始文档的位置; 检测部，其将从第一颜色到原稿的扫描方向的第一图像信号和从第二颜色向原稿的扫描方向上的第二图像信号进行监视，并且检测用于提取与第一颜色相对应的图像信号的位置 基于在第一图像信号或第二图像信号中的任一个发生的变化在原始文档上反射的光。

    Test circuit for large scale integrated circuits on a wafer
    4.
    发明授权
    Test circuit for large scale integrated circuits on a wafer 失效
    用于晶圆上大规模集成电路的测试电路

    公开(公告)号：US5446395A

    公开(公告)日：1995-08-29

    申请号：US124071

    申请日：1993-09-21

    Applicant: Junichi Goto

    Inventor： Junichi Goto

    IPC: G01R31/28 ,  G01R31/3185 ,  H01L21/66

    CPC classification number: G01R31/318505 ,  G01R31/2884 ,  G01R31/318511

    Abstract: A test circuit for conducting a simultaneous test of a plurality of integrated circuits provided in dicing regions of a wafer. The test circuit has a pattern generator electrically connected to the integrated circuits through first interconnections for generating input signal patterns and subsequent transmission thereof to each of the integrated circuits and pattern compressor/comparator electrically connected to the integrated circuits through second interconnections for analyzing output signals fetched from the integrated circuits so as to conduct a simultaneous test of a plurality of the integrated circuits.

    Abstract translation: 一种测试电路，用于对设置在晶片切割区域中的多个集成电路进行同时测试。 测试电路具有通过第一互连电连接到集成电路的模式发生器，用于产生输入信号模式，并随后通过第二互连电路连接到集成电路和图形压缩器/比较器，以分析输出信号 从集成电路中进行多个集成电路的同时测试。

    Method of computer-assisted design of integrated circuit chips, and library of delay time values for computer-assisted design of such chips
    5.
    发明授权
    Method of computer-assisted design of integrated circuit chips, and library of delay time values for computer-assisted design of such chips 失效
    计算机辅助设计集成电路芯片的方法，以及这种芯片的计算机辅助设计的延迟时间值库

    公开(公告)号：US07051314B2

    公开(公告)日：2006-05-23

    申请号：US10326379

    申请日：2002-12-23

    Applicant: Junichi Goto

    Inventor： Junichi Goto

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G03F7/70425 ,  G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of placing integrated circuit chips on a wafer uses a library of average delay time values of logic gates. Exposure-dependent delay time values of the logic gates, which result from exposure of a unit area to a beam of radiation, are additionally stored in the library. These delay time values are detected by successively exposing unit areas of a test wafer to a beam of radiation as a function of relative positions of each integrated circuit chip within the unit exposure area. In a modified embodiment, only one integrated circuit chip within each unit area is exposed to the radiation beam, and the exposure-dependent delay time values are detected as a function of position within the exposed integrated circuit chip or as a function of distance from the center of the each unit area.

    Abstract translation: 将集成电路芯片放置在晶片上的方法使用逻辑门的平均延迟时间值的库。 在图书馆中还附加存储由曝光单位区域到辐射束产生的逻辑门的曝光相关延迟时间值。 这些延迟时间值是通过将测试晶片的单位面积依次暴露于单位曝光区域内的每个集成电路芯片的相对位置的函数来将辐射束连续曝光来检测的。 在修改的实施例中，在每个单位区域内只有一个集成电路芯片暴露于辐射束，并且依赖于暴露的集成电路芯片中的曝光相关延迟时间值作为位置的函数被检测，或作为距离 每个单位面积的中心。

    Digital processor with instruction memory of reduced storage size
    8.
    发明授权
    Digital processor with instruction memory of reduced storage size 失效
    具有减少存储大小的指令存储器的数字处理器

    公开(公告)号：US5410659A

    公开(公告)日：1995-04-25

    申请号：US47579

    申请日：1993-04-13

    Applicant: Junichi Goto

    Inventor： Junichi Goto

    IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/3822 ,  G06F9/30145

    Abstract: A digital processor has a data processing unit having arithmetic/logic operation circuits, an instruction memory for storing an instruction word, and an instruction decoder for decoding the instruction word read from the instruction memory and outputting the control signals respectively to the arithmetic/logic operation circuits. Each instruction word has at least a first control field and a second control field. The instruction decoder has two decoding circuits. Each of the decoding circuits corresponds to each group of the arithmetic/logic operation circuits, receives the instruction word for decoding the second control field into a control signal and outputs an ENABLE signal. The ENABLE signal from the first decoding circuit is applied to the second decoding circuit, and the ENABLE signal from the second decoding circuit is applied to the first decoding circuit. Only one of the first and second decoding circuits outputs a control signal at a time.

    Abstract translation: 数字处理器具有具有算术/逻辑运算电路的数据处理单元，用于存储指令字的指令存储器和用于对从指令存储器读取的指令字进行解码的指令译码器，分别将控制信号输出到运算/逻辑运算 电路。 每个指令字具有至少第一控制字段和第二控制字段。 指令译码器具有两个解码电路。 每个解码电路对应于每组算术/逻辑运算电路，将用于将第二控制场解码的指令字接收到控制信号中，并输出ENABLE信号。 来自第一解码电路的ENABLE信号被施加到第二解码电路，并且来自第二解码电路的ENABLE信号被施加到第一解码电路。 第一和第二解码电路中只有一个一次输出控制信号。

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