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    High speed cross point switch routing circuit with word-synchronous serial back plane
    1.
    发明授权
    High speed cross point switch routing circuit with word-synchronous serial back plane 失效

    公开(公告)号：US06377575B1

    公开(公告)日：2002-04-23

    申请号：US09129662

    申请日：1998-08-05

    申请人： John P. Mullaney ,  Gary M. Lee

    发明人： John P. Mullaney ,  Gary M. Lee

    IPC分类号： H04L1250

    CPC分类号： H04L12/5601 ,  H04J3/0685 ,  H04L7/04 ,  H04L49/1576 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5674 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L2012/5684 ,  H04Q11/0478

    摘要： An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

    High speed cross point switch routing circuit with word-synchronous serial back plane
    2.
    发明授权
    High speed cross point switch routing circuit with word-synchronous serial back plane 有权
    具有字同步串行背板的高速交叉点开关路由电路

    公开(公告)号：US06700886B2

    公开(公告)日：2004-03-02

    申请号：US10047166

    申请日：2002-01-14

    申请人： John P. Mullaney ,  Gary M. Lee

    发明人： John P. Mullaney ,  Gary M. Lee

    IPC分类号： H04L1250

    CPC分类号： H04L12/5601 ,  H04J3/0685 ,  H04L7/04 ,  H04L49/1576 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5674 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L2012/5684 ,  H04Q11/0478

    摘要： An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

    摘要翻译： 异步串行交叉点开关与多个收发器电路中的每一个字字同步。 交叉点开关电路产生主位时钟和主字时钟信号。 收发器电路使用时钟和数据恢复电路从输入的高速串行数据流中恢复主位时钟信号。 恢复的位时钟信号用作定时信号，数据被串行化并发送到交叉点开关电路。 发送到开关电路的数据流被锁定到主位时钟信号，使得串行数据流仅需要用数据恢复电路进行相位调整。 为了恢复字定时，开关电路在链路初始化期间向对收发器发出对准字。 收发器执行字对齐并建立本地字锁。 然后使用本地字时钟将对准字重新发给开关电路。 开关电路将接收的字时钟的边界与主字时钟进行比较，如果未对准，收发器将其发送的字移位一位，然后重试。 必要边缘转换密度由开销比特提供，开销比特还指示在收发机和开关电路之间所确定的特殊命令字。 流量控制信息使用开销位置从接收收发器路由到发送收发器，以便断言即将接收或不准备接收的流量控制信号。 开销比特还提供关于连接请求和其他信息的信息。

    High speed cross point switch routing circuit with word-synchronous serial back plane
    3.
    发明授权
    High speed cross point switch routing circuit with word-synchronous serial back plane 失效

    公开(公告)号：US06801518B2

    公开(公告)日：2004-10-05

    申请号：US10074106

    申请日：2002-02-12

    申请人： John P. Mullaney ,  Gary M. Lee

    发明人： John P. Mullaney ,  Gary M. Lee

    IPC分类号： H04L1250

    CPC分类号： H04L12/5601 ,  H04J3/0685 ,  H04L7/04 ,  H04L49/1576 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5674 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L2012/5684 ,  H04Q11/0478

    摘要： An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.

    Logic gates for reducing power consumption of gallium arsenide integrated circuits
    6.
    发明授权
    Logic gates for reducing power consumption of gallium arsenide integrated circuits 失效
    用于降低砷化镓集成电路功耗的逻辑门

    公开(公告)号：US6078194A

    公开(公告)日：2000-06-20

    申请号：US558108

    申请日：1995-11-13

    申请人： Gary M. Lee

    发明人： Gary M. Lee

    IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K19/00 ,  H03K19/094 ,  H03K19/0952

    CPC分类号： H03K19/0016 ,  H03K19/09429 ,  H03K19/0952 ,  H03K3/012 ,  H03K3/0372

    摘要： A method and apparatus for reducing power consumption by gallium arsenide integrated circuits divides the integrated circuit into higher and lower frequency sections. The high frequency sections require a substantial portion of the system clock period to resolve their longest combinatorial paths. The lower frequency sections require a relatively small portion of the system clock period to resolve their longest combinatorial logic paths. The combinatorial logic paths of each of such lower frequency sections are designed using logic gates which are capable of being decoupled from the chip power supply by way of a power enable input. Edge triggered memory circuits such as flip-flops are also designed using the reduced power logic gates, except for their cross-coupled outputs so that they may retain their state. A dual-output one-shot multivibrator is used to generate the power enable signal used to couple and decouple the logic gates of each lower frequency section from the chip power supply, as well as the clock pulse with which to clock the flip-flops of the lower frequency section. The one-shot generates these control signals based on the positive edge of the system clock. The lower frequency sections thus dissipate virtually no power except during that portion of the system clock period necessary to resolve their longest combinatorial paths.

    摘要翻译： 用于降低砷化镓集成电路的功耗的方法和装置将集成电路分为更高和更低频率的部分。 高频部分需要系统时钟周期的大部分来解决其最长的组合路径。 较低频率部分需要系统时钟周期的较小部分来解决其最长的组合逻辑路径。 这些低频段中的每一个的组合逻辑路径使用能够通过功率使能输入与芯片电源分离的逻辑门来设计。 诸如触发器之类的边缘触发存储器电路也使用减少功率逻辑门来设计，除了它们的交叉耦合输出，使得它们可以保持其状态。 双输出单稳态多谐振荡器用于产生功率使能信号，用于将芯片电源中每个较低频率部分的逻辑门极耦合和去耦，以及时钟脉冲 较低频段。 一次性根据系统时钟的上升沿产生这些控制信号。 因此，除了解决其最长组合路径所需的系统时钟周期的那部分之外，较低频率部分几乎没有功率消耗。