摘要:
An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.
摘要:
An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.
摘要:
An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial data stream using a clock and data recovery circuit. The recovered bit clock signal is used as a timing signal by which data is serialized and transmitted to the crosspoint switch circuit. The data stream transmitted to the switch circuit is frequency locked to the master bit clock signal, such that the serial data stream need only be phase adjusted with a data recovery circuit. To recover word timing, the switch circuit issues alignment words to the transceivers during link initialization. The transceivers perform word alignment and establish a local word lock. Alignment words are then reissued to the switch circuit using the local word clock. The switch circuit compares the boundary of the received word clock to the master word clock and, if misaligned, the transceiver shifts its transmitted word by one bit and retries. Necessary edge transition density is provided by overhead bits which also designate special command words asserted between a transceiver and a switch circuit. Flow control information is routed from a receiving transceiver back to the transmitting transceiver using the overhead bits in order to assert a ready-to-receive or a not-ready-to-receive flow control signal. The overhead bits additionally provide information regarding connection requests and other information.
摘要:
Disclosed are a process and intermediates of the formulae ##STR1## wherein X.sup.- is halide, BF.sub.4.sup.-, R.sup.3 SO.sub.3.sup.-, wherein R.sup.3 is C.sub.1 -C.sub.6 alkyl, CF.sub.3, C.sub.1 -C.sub.6 alkylphenyl or phenyl, and Q is a group of the formula ##STR2## wherein R is C.sub.1 -C.sub.6 alkyl; useful for preparing benzazepine intermediates of the formula ##STR3## These benzazepine intermediates are useful for preparing benzazepines having activity as selective D1 receptor antagonists.
摘要:
The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.
摘要:
A method and apparatus for reducing power consumption by gallium arsenide integrated circuits divides the integrated circuit into higher and lower frequency sections. The high frequency sections require a substantial portion of the system clock period to resolve their longest combinatorial paths. The lower frequency sections require a relatively small portion of the system clock period to resolve their longest combinatorial logic paths. The combinatorial logic paths of each of such lower frequency sections are designed using logic gates which are capable of being decoupled from the chip power supply by way of a power enable input. Edge triggered memory circuits such as flip-flops are also designed using the reduced power logic gates, except for their cross-coupled outputs so that they may retain their state. A dual-output one-shot multivibrator is used to generate the power enable signal used to couple and decouple the logic gates of each lower frequency section from the chip power supply, as well as the clock pulse with which to clock the flip-flops of the lower frequency section. The one-shot generates these control signals based on the positive edge of the system clock. The lower frequency sections thus dissipate virtually no power except during that portion of the system clock period necessary to resolve their longest combinatorial paths.
摘要:
Disclosed are a process and intermediates of the formula ##STR1## wherein R is --CH.sub.3 or --C(O)--OR.sup.1, and R.sup.1 is C.sub.1 -C.sub.6 alkyl or --CH.sub.2 C.sub.6 H.sub.5 ; or the formula ##STR2## wherein: R.sup.2 is H or OH, R is --C(O)OR.sup.1 and R.sup.1 is C.sub.1 -C.sub.6 alkyl or --CH.sub.2 C.sub.6 H.sub.5, or where R.sup.2 is H, R can also be CH.sub.3 ; for preparing benzazepine intermediates of the formula ##STR3## The benzazepine intermediates are useful for preparing benzazepines having activity as selective D1 receptor antagonists.
摘要翻译:公开了式(IMAGE)的方法和中间体,其中R是-CH 3或-C(O)-OR 1,R 1是C 1 -C 6烷基或-CH 2 C 6 H 5; 或其中:R 2是H或OH,R是-C(O)OR 1,R 1是C 1 -C 6烷基或-CH 2 C 6 H 5,或者其中R 2是H,R也可以是CH 3; 用于制备下式的苯并氮杂中间体苯并吖庚因中间体可用于制备具有作为选择性D1受体拮抗剂活性的苯并氮杂。
摘要:
A high performance logic family for GaAs Enhancement/Depletion mode MESFETs is disclosed. The inventive logic family exhibits a large noise margin with little sacrifice in speed/power performance.
摘要:
The present process provides a improved method for the preparation of alkylsulfanyl substituted triazoles 2 which are useful intermediates in a new process for the preparation of triazolones 20.
摘要:
In an illustrative embodiment, the present invention describes the synthesis of the following compound and similar compounds, in high stereochemical purity by a novel stereoselective alkylation process: