公开(公告)号：US5757799A

公开(公告)日：1998-05-26

申请号：US586124

申请日：1996-01-16

申请人： George S. LaRue

发明人： George S. LaRue

IPC分类号： H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L49/102 ,  H04L49/201 ,  H04L49/3027

摘要： A high speed packet switch which is inherently non-blocking, requires a minimum amount of buffering, is modular and degrades gracefully with failures. The output destination buffers can each absorb data at the full switch rate to avoid contention and they are filled evenly to minimize buffer size. The architecture only requires few parts types (multiplexers, demultiplexers and crosspoint switches) to operate at high speeds. The output list offers considerable flexibility in the way the data is output, whether it is by priority and/or by time division multiplexed sub destinations.

摘要翻译： 高速分组交换机本质上是非阻塞的，需要最小量的缓冲，是模块化的，并且随着故障而正常地降级。 输出目标缓冲区可以以完全切换速率吸收数据，以避免争用，并且它们被均匀地填充以最小化缓冲区大小。 该架构只需要很少的部件类型（多路复用器，解复用器和交叉点开关）以高速运行。 输出列表在数据输出方式上提供了相当大的灵活性，无论是按优先级还是/或通过时分复用的子目的地。

公开(公告)号：US5144230A

公开(公告)日：1992-09-01

申请号：US618050

申请日：1990-11-26

申请人： Mehdi Katoozi ,  George S. LaRue

发明人： Mehdi Katoozi ,  George S. LaRue

IPC分类号： G06F11/18 ,  G06F11/27

CPC分类号： G06F11/184 ,  G06F11/27 ,  G06F2201/805

摘要： A system for performing a self test on a circuit without interrupting its normal function. Several embodiments of a self-test system (10, 60, 80, 100, 120) are disclosed, each of which include a test generator (22) that generates a test signal selectively applied to a circuit under test (CUT) (12, 122). The CUT produces an output signal that is analyzed to determine whether the circuit is operating properly. In several of the embodiments, a signature analyzer (44) compares the signature of the output signal to a predetermined expected signature after a sequence of test vectors have been performed on the CUT. In a fault-tolerant embodiment of the self-test system (100), a plurality of CUTs are evaluated in respect to the output signal produced thereby, both when operating to process a normal input signal and, when processing a test signal. A voter (108) selects an output signal for use by a primary signal utilization device (42) from among the output signals of the redundant CUTs and thus determines whether one of the redundant circuits has failed to operate properly. In each embodiment, the self test can occur either during multiple system clock cycles when the circuit is available, or during a portion of each system clock cycle in which the circuit under test is not required to perform its normal function. In another embodiment involving a first circuit portion (124) that produces an intermediate data state that must be held between successive clock cycles for use by a second circuit portion (126), a latch (130) is used to bypass a latch (128) within the circuit under test, so that both portions of the circuit are evaluated without disrupting operation of the signal utilization device.

摘要翻译： 一种用于在不中断其正常功能的情况下在电路上执行自检的系统。 公开了自检系统（10,60,80,100,120）的几个实施例，每个实施例包括产生选择性地施加到被测电路（CUT）的测试信号的测试发生器（22） 122）。 CUT产生一个被分析的输出信号，以确定电路是否正常工作。 在几个实施例中，签名分析器（44）在对CUT执行了一系列测试向量之后，将输出信号的签名与预定的预期签名进行比较。 在自检系统（100）的容错实施例中，当处理正常输入信号和处理测试信号时，对于由此产生的输出信号，对多个CUT进行评估。 选民（108）从冗余CUT的输出信号中选择由主要信号利用装置（42）使用的输出信号，从而确定冗余电路中的一个是否不能正常工作。 在每个实施例中，自检可以在电路可用的多个系统时钟周期期间发生，或者在每个系统时钟周期的一部分期间，其中不需要测试电路来执行其正常功能。 在另一个实施例中，涉及产生中间数据状态的第一电路部分（124），该中间数据状态必须保持在由第二电路部分（126）使用的连续时钟周期之间，锁存器（130）用于绕过锁存器（128） 在测试电路内，使得电路的两个部分被评估，而不中断信号利用装置的操作。

公开(公告)号：US5027007A

公开(公告)日：1991-06-25

申请号：US336709

申请日：1989-04-12

申请人： George S. LaRue ,  Timothy J. Williams

发明人： George S. LaRue ,  Timothy J. Williams

IPC分类号： H03K19/0952 ,  H03K19/21

CPC分类号： H03K19/0952 ,  H03K19/217

摘要： An FFL/QFL family of logic gates is disclosed, preferably implemented with GaAs MESFET devices and providing enhanced speed-power characteristics. Although a number of gate configurations are disclosed, a NOR gate 26 constructed in accordance with this invention includes a pair of normally OFF input transistors Q1 and Q7, which receive inputs A and B. Current sources Q2 and Q3 couple the transistors to the supply voltage V.sub.DD and ground, respectively. A control transistor Q6 is also coupled to the input and source transistors. An output section 30 responds to the combined operation of transistors Q1, Q2, Q3, Q6, and Q7 to produce an output C in accordance with conventional NOR logic. More particularly, upon application of a high logic input A or B to transistors Q1 and/or Q7, transistors Q1 and/or Q7 and Q6 turn ON and the output C is at a logic low level. If both inputs A and B are low, however, transistors Q1, Q6, and Q7 remain OFF, and the output C is at a high logic level. Use of the control transistor Q6 allows smaller input transistors Q1 and Q7 and current source Q3 to be used, increasing the integration level and gate speed via decreased capacitance.

摘要翻译： 公开了一种FFL / QFL逻辑门系列，优选地利用GaAs MESFET器件实现并提供增强的速度功率特性。 尽管公开了多个栅极配置，但是根据本发明构造的或非门26包括一对正常关闭的输入晶体管Q1和Q7，其接收输入A和B.电流源Q2和Q3将晶体管耦合到电源电压 VDD和接地。 控制晶体管Q6还耦合到输入和晶体管。 输出部分30响应于晶体管Q1，Q2，Q3，Q6和Q7的组合操作，以产生根据常规NOR逻辑的输出C. 更具体地，当将高逻辑输入A或B施加到晶体管Q1和/或Q7时，晶体管Q1和/或Q7和Q6导通，输出C处于逻辑低电平。 然而，如果两个输入A和B都为低电平，则晶体管Q1，Q6和Q7保持OFF，输出C处于高逻辑电平。 使用控制晶体管Q6可以使用更小的输入晶体管Q1和Q7以及电流源Q3，通过降低电容来增加积分电平和栅极速度。

公开(公告)号：US4628406A

公开(公告)日：1986-12-09

申请号：US736205

申请日：1985-05-20

申请人： Kenneth R. Smith ,  Kent H. Johnston ,  George S. LaRue ,  Robert A. Mueller ,  Steven A. Tabor

发明人： Kenneth R. Smith ,  Kent H. Johnston ,  George S. LaRue ,  Robert A. Mueller ,  Steven A. Tabor

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/538 ,  H05K1/11

CPC分类号： H01L24/72 ,  H01L23/5387 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3011 ,  Y10T29/4913

摘要： An integrated circuit package comprises at least two integrated circuit chips each having a plurality of contact pads arranged in a first pattern on the interconnect face of the chip, and an elastic sheet-form interconnect member. The interconnect member has at least two main face areas, associated with the chips respectively, and comprises dielectric material and conductor runs supported by the dielectric material in mutually electrically insulated relationship and having termination points arranged in at least two second patterns at the main face areas respectively and corresponding with the first patterns respectively. The interconnect face of each is in confronting relationship with the associated main face area of the interconnect member, and the contact pads of the chip and the termination points of the associated main face area are in mutually registering relationship. A metallurgical bond is formed between each contact pad and the corresponding termination point. The assembly of the interconnect member and the integrated circuit chips is placed between, and in pressure contact with, first and second essentially rigid enclosure members, with the first enclosure member in thermally-conductive contact with the back face of at least one of the chips and being made of a material that has good thermal conductivity.

摘要翻译： 集成电路封装包括至少两个集成电路芯片，每个集成电路芯片具有在芯片的互连面上以第一图案布置的多个接触焊盘和弹性片状互连构件。 互连构件具有分别与芯片相关联的至少两个主面区域，并且包括由电介质材料以相互电绝缘的关系支撑的介电材料和导体行程，并且具有以主要面积区域中的至少两个第二图案布置的终端点 分别对应于第一模式。 每个的互连面与互连构件的相关联的主面区域面对面，并且芯片的接触焊盘和相关主面区域的终端点处于相互对准的关系。 在每个接触垫和相应的终端点之间形成冶金结合。 互连构件和集成电路芯片的组合被放置在与第一和第二基本上刚性的外壳构件压力接触之间，其中第一外壳构件与至少一个芯片的背面导热接触 并且由具有良好导热性的材料制成。

公开(公告)号：US5777505A

公开(公告)日：1998-07-07

申请号：US591738

申请日：1996-01-25

申请人： George S. LaRue

发明人： George S. LaRue

IPC分类号： H03K17/00 ,  H03K17/693 ,  H03K19/00

CPC分类号： H03K19/0013 ,  H03K17/693 ,  H03K2217/0036

摘要： A configurable circuit includes a first subcircuit (206) and a second subcircuit (410) each having a static power dissipation. A first bias circuit (402), coupled to the first subcircuit (206), provides a first bias level to the first subcircuit (206). Similarly, a second bias circuit (412), coupled to the second subcircuit (410), provides a second bias level to the second subcircuit (410). A logic circuit (403) is coupled to the first bias circuit (402) and the second bias circuit (412) and selectively provides a first signal to the first bias circuit (402). In response to the first signal, the first bias circuit (402) changes the bias level provided to the first subcircuit (206). The changed bias level disables the first subcircuit (206), substantially reducing the static power dissipation of the first subcircuit (206) while allowing the second subcircuit (410) to continue operating. In one embodiment, the circuit is a crosspoint switch with multiplexer subcircuits. The logic circuit (403) receives configuration information from an external controller and configures the multiplexers in response to the configuration information. The logic circuit can selectively disable one or more of the multiplexers to substantially reduce the static power dissipation of the selected multiplexers.

摘要翻译： 可配置电路包括每个具有静态功耗的第一子电路（206）和第二子电路（410）。 耦合到第一子电路（206）的第一偏置电路（402）向第一子电路（206）提供第一偏置电平。 类似地，耦合到第二子电路（410）的第二偏置电路（412）向第二子电路（410）提供第二偏置电平。 逻辑电路（403）耦合到第一偏置电路（402）和第二偏置电路（412），并且选择性地向第一偏置电路（402）提供第一信号。 响应于第一信号，第一偏置电路（402）改变提供给第一子电路（206）的偏置电平。 改变的偏置电平禁用第一子电路（206），大大降低第一子电路（206）的静态功耗，同时允许第二子电路（410）继续工作。 在一个实施例中，电路是具有多路复用器子电路的交叉点开关。 逻辑电路（403）从外部控制器接收配置信息，并根据配置信息配置多路复用器。 逻辑电路可以选择性地禁用多路复用器中的一个或多个，以显着降低所选多路复用器的静态功耗。

公开(公告)号：US4798978A

公开(公告)日：1989-01-17

申请号：US44519

申请日：1987-04-30

申请人： Gary M. Lee ,  Charles M. Lee ,  George S. LaRue

发明人： Gary M. Lee ,  Charles M. Lee ,  George S. LaRue

IPC分类号： H03K19/017 ,  H03K19/0952 ,  H03K19/094

CPC分类号： H03K19/0952 ,  H03K19/01721

摘要： A high performance logic family for GaAs Enhancement/Depletion mode MESFETs is disclosed. The inventive logic family exhibits a large noise margin with little sacrifice in speed/power performance.

摘要翻译： 公开了一种用于GaAs增强/消耗模式MESFET的高性能逻辑系列。 本发明的逻辑系列表现出较大的噪声容限，在速度/功率性能方面几乎没有牺牲。

公开(公告)号：US4716311A

公开(公告)日：1987-12-29

申请号：US726864

申请日：1985-04-25

申请人： William H. Davenport ,  Gary D. McCormack ,  George S. LaRue

发明人： William H. Davenport ,  Gary D. McCormack ,  George S. LaRue

IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0952 ,  H03K17/16 ,  H03K19/094 ,  H03K19/12

CPC分类号： H03K19/0952 ,  H03K19/00384 ,  H03K19/017

摘要： An integrated logic circuit comprises a direct coupled FET logic input stage and a super buffer logic output stage. The input stage comprises a depletion-mode FET having its drain connected to a first reference potential level and having its gate and source connected together, and a first enhancement mode FET structure having its drain connected to the source of the depletion-mode FET, its source connected to a second, lower reference potential level and having at least one gate connected to receive an input logical signal. The super buffer logic output stage comprises a second enhancement mode FET structure that is essentially identical to the first enhancement mode FET structure, the source of the second enhancement mode FET structure being connected to the second reference potential level and the gate of the second enhancement mode FET structure being connected to the gate of the first enhancement mode FET structure. The output stage also comprises a controllable current source connected between the source of the depletion-mode FET and the drain of the second enhancement mode FET structure, for providing drain current to the second enhancement mode FET structure when the potential of the drain of the first enhancement mode FET structure exceeds a predetermined level, and depriving the second enhancement mode FET structure of drain current when the drain of the first enhancement mode FET structure is below the predetermined potential level.

摘要翻译： 集成逻辑电路包括直接耦合FET逻辑输入级和超级缓冲器逻辑输出级。 输入级包括其漏极连接到第一参考电位并且其栅极和源极连接在一起的耗尽型FET，以及其漏极连接到耗尽型FET的源极的第一增强型FET结构，其 源极连接到第二较低参考电位电平并具有至少一个栅极连接以接收输入逻辑信号。 超级缓冲器逻辑输出级包括与第一增强型FET结构基本相同的第二增强型FET结构，第二增强型FET结构的源极连接到第二参考电位电平和第二增强模式的栅极 FET结构连接到第一增强型FET结构的栅极。 输出级还包括连接在耗尽型FET的源极和第二增强型FET结构的漏极之间的可控电流源，用于当第一增强型FET结构的漏极的电位提供到第二增强型FET结构时， 增强型FET结构超过预定电平，并且当第一增强型FET结构的漏极低于预定电位电平时，剥夺第二增强型FET结构的漏极电流。