公开(公告)号：US06453360B1

公开(公告)日：2002-09-17

申请号：US09259765

申请日：1999-03-01

申请人： Shimon Muller ,  Denton E. Gentry, Jr. ,  John E. Watkins ,  Linda T. Cheng

发明人： Shimon Muller ,  Denton E. Gentry, Jr. ,  John E. Watkins ,  Linda T. Cheng

IPC分类号： G06F1300

CPC分类号： H04L49/9094 ,  H04L29/06 ,  H04L47/2441 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9063 ,  H04L49/9078 ,  H04L69/16 ,  H04L69/161 ,  H04L69/167 ,  H04L69/18 ,  H04L69/22 ,  H04L69/26

摘要： A high performance network interface is provided for receiving a packet from a network and transferring it to a host computer system. A header portion of a received packet is parsed by a parser module to determine the packet's compatibility with, or conformance to, one or more pre-selected protocols. If compatible, a number of processing functions may be performed to increase the efficiency with which the packet is handled. In one function, a re-assembly engine re-assembles, in a re-assembly buffer, data portions of multiple packets in a single communication flow or connection. Header portions of such packets are stored in a header buffer. An incompatible packet may be stored in another buffer. In another function, a packet batching module determines when multiple packets in one flow are transferred to the host computer system, so that their header portions are processed collectively rather than being interspersed with headers of other flows' packets. In yet another function, the processing of packets through their protocol stacks is distributed among multiple processors by a load distributor, based on their communication flows. A flow database is maintained by a flow database manager to reflect the creation, termination and activity of flows. A packet queue stores packets to await transfer to the host computer system, and a control queue stores information concerning the waiting packets. If the packet queue becomes saturated with packets, a random packet may be discarded. An interrupt modulator may modulate the rate at which interrupts associated with packet arrival events are issued to the host computer system.

摘要翻译： 提供了一种高性能网络接口，用于从网络接收分组并将其传送到主机系统。 接收到的分组的报头部分由解析器模块解析以确定分组与一个或多个预选协议的兼容性或符合一个或多个预选协议。 如果兼容，则可以执行多个处理功能以提高处理分组的效率。 在一个功能中，重新组装引擎在重新组装缓冲器中重新组装单个通信流或连接中的多个分组的数据部分。 这些分组的报头部分被存储在报头缓冲器中。 不兼容的数据包可能存储在另一个缓冲区中。 在另一个功能中，分组批处理模块确定一个流中的多个分组何时被传送到主计算机系统，使得它们的头部部分被集体处理，而不是散布在其他流的分组的头部。 在另一个功能中，通过它们的协议栈对分组的处理由负载分配器基于它们的通信流分布在多个处理器之间。 流数据库由流数据库管理器维护，以反映流的创建，终止和活动。 分组队列存储分组以等待传送到主计算机系统，并且控制队列存储关于等待分组的信息。 如果分组队列变得饱和，则随机分组可能被丢弃。 中断调制器可以调制与主机计算机系统发出与分组到达事件相关联的中断的速率。

公开(公告)号：US5854911A

公开(公告)日：1998-12-29

申请号：US675263

申请日：1996-07-01

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F13/00 ,  G06F9/38 ,  H04L12/56 ,  H04Q11/04 ,  G06F13/12 ,  G06F13/14

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5681

摘要： A prefetch apparatus optimizes bandwidth in a computer network by prefetch accessing data blocks prior to their demand in an ATM network thereby effectively reducing memory read latency. The method of the preferred embodiment includes the steps of: 1) computing a prefetch address of a next sequential data block given an address of a requested data block; 2) comparing a current request address against a previously computed prefetch address; and 3) generating a hit/miss indication corresponding to whether the current request address matches the previously computed prefetch address.

摘要翻译： 预取装置通过在ATM网络中的需求之前预取访问数据块来优化计算机网络中的带宽，从而有效地减少存储器读取延迟。 优选实施例的方法包括以下步骤：1）计算给定所请求数据块的地址的下一个顺序数据块的预取地址; 2）将当前请求地址与先前计算的预取地址进行比较; 以及3）产生与当前请求地址是否匹配先前计算的预取地址相对应的命中/未命中指示。

公开(公告)号：US4055935A

公开(公告)日：1977-11-01

申请号：US655866

申请日：1976-02-06

申请人： William R. Malion ,  John E. Watkins

发明人： William R. Malion ,  John E. Watkins

IPC分类号： A01D34/68 ,  F16D67/02 ,  A01D75/18 ,  A01D69/10 ,  H02G11/00

CPC分类号： A01D34/6812 ,  F16D67/02 ,  A01D2101/00

摘要： A lawnmower has an improved clutch-brake mechanism interposed between the engine drive shaft and the rotating blade to stop the blade except when an operator tensions a control cable. The clutch-brake includes cylindrical input and output members selectively drivingly coupled by a clutch spring wound around both members. A control sleeve positioned around the clutch spring connects with the input end of the clutch spring. When the control sleeve is braked, the clutch spring releases its grip on the input member and the output is no longer driven. A coiled brake band extends around the control sleeve to selectively effect this braking action. An improved floating mount is provided for the brake band. An improved lost-motion connection is provided between the control sleeve and the output member to limit the twisting of the clutch spring. An optional slip clutch is provided for connecting the output member to the blade.

摘要翻译： 割草机具有改进的离合器制动机构，其插入在发动机驱动轴和旋转叶片之间，以便除了当操作者拉紧控制缆索之后停止叶片。 离合器制动器包括通过缠绕在两个构件上的离合器弹簧选择性地驱动联接的圆柱形输入和输出构件。 定位在离合器弹簧周围的控制套筒与离合器弹簧的输入端连接。 当控制套筒被制动时，离合器弹簧释放其对输入构件的夹紧，并且输出不再被驱动。 线圈制动带围绕控制套筒延伸以选择性地实现该制动动作。 为制动带提供改进的浮动安装。 在控制套筒和输出构件之间提供改进的空动连接以限制离合器弹簧的扭转。 提供了可选的滑动离合器用于将输出构件连接到叶片。

公开(公告)号：US08225007B2

公开(公告)日：2012-07-17

申请号：US12355856

申请日：2009-01-19

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F13/14 ,  G06F9/50

CPC分类号： G06F12/0284

摘要： A method for reducing address space in a shared virtualized I/O device includes allocating hardware resources including variable resources and permanent resources, to one or more functions. The method also includes allocating address space for an I/O mapping of the resources in a system memory, and assigning a respective portion of that address space for each function. The method further includes assigning space within each respective portion for variable resources available for allocation to the function to which the respective portion is assigned, and further assigning space within each respective portion for a set of permanent resources that have been allocated to the function to which the respective portion is assigned. The method further includes providing a translation table having a plurality of entries, and storing within each entry of the translation table, a different internal address of a permanent resource that has been allocated to a particular function.

摘要翻译： 一种用于减少共享虚拟化I / O设备中的地址空间的方法包括将包括可变资源和永久资源的硬件资源分配给一个或多个功能。 该方法还包括为系统存储器中的资源的I / O映射分配地址空间，以及为每个功能分配该地址空间的相应部分。 该方法还包括在每个相应部分内分配可用于分配给分配给相应部分的功能的可变资源的空间，以及为已经分配给该功能的一组永久资源进一步分配每个相应部分内的空间 分配相应的部分。 该方法还包括提供具有多个条目的转换表，并且在转换表的每个条目内存储已被分配给特定功能的永久资源的不同内部地址。

公开(公告)号：US20110296256A1

公开(公告)日：2011-12-01

申请号：US12787001

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

发明人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

IPC分类号： G06F11/07

CPC分类号： G06F11/0745 ,  G06F11/0724 ,  G06F11/0766

摘要： An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.

摘要翻译： I / O设备包括可以接收和处理由多个处理单元发送的事务分组的主机接口，每个处理单元对应于相应的根复合体。 主机接口包括具有在硬件中实现的错误逻辑的错误处理单元，其可以在接收到每个分组时确定每个事务分组是否具有错误并存储与任何检测到的错误相对应的信息。 错误处理单元可以包括错误处理器，其可被配置为执行错误处理指令以基于该信息来确定任何错误处理操作。 错误处理器还可以生成和发送一个或多个指令操作，每个指令操作对应于特定的错误处理操作。 错误处理单元还可以包括可以执行一个或多个指令操作以执行特定错误处理操作的错误处理单元。

公开(公告)号：US20110106981A1

公开(公告)日：2011-05-05

申请号：US12611694

申请日：2009-11-03

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F3/00

CPC分类号： G06F13/4221

摘要： The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region.

摘要翻译： 所描述的实施例提供用于访问配置空间寄存器（CSR）的值的系统。 该系统包括具有地址输入和CSR数据输出的CSR数据存储机制。 CSR数据存储机制包括存储多个存储器位置的存储器，用于存储针对相应设备的功能的CSR的真实值或实际值。 在这些实施例中，存储器位置被划分为至少一个共享区域和至少一个唯一区域。 在这些实施例中，响应于接收地址输入上的存储器位置的地址，CSR数据存储机构访问对应共享区域或唯一区域中的存储器位置中的CSR值。

公开(公告)号：US20110072172A1

公开(公告)日：2011-03-24

申请号：US12562319

申请日：2009-09-18

申请人： Elisa Rodrigues ,  John E. Watkins

发明人： Elisa Rodrigues ,  John E. Watkins

IPC分类号： G06F13/14 ,  G06F3/00

CPC分类号： G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808

摘要： An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.

摘要翻译： I / O设备包括耦合到多个硬件资源的主机接口。 主机接口包括可以接收和处理由多个处理单元发送的多个事务层分组的事务层分组（TLP）处理单元。 每个处理单元可以对应于相应的根复合体。 TLP处理单元可以识别与每个事务层分组对应的事务类型和处理单元，并且根据事务类型和处理单元将每个事务层分组存储在存储器内。 TLP处理单元可以基于使用仲裁方案的一组公平标准从存储器中选择一个或多个事务层分组来进行进程调度。 TLP处理单元还可以基于附加标准进一步选择和调度事务层分组以供下游应用硬件处理。

公开(公告)号：US08527745B2

公开(公告)日：2013-09-03

申请号：US12632415

申请日：2009-12-07

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F15/177 ,  G06F9/00 ,  G06F11/00

CPC分类号： G06F13/102

摘要： An I/O device includes a host interface configured to process function level reset (FLR) requests in a specified amount of time. The host interface includes a control unit and groups of configuration space registers, each group corresponding to a function. The host interface also includes application availability registers, each associated with a respective function, and which may indicate whether application hardware within the respective function is available for access by a corresponding application device driver. The I/O device also includes application hardware resources associated with a respective function. In response to receiving an FLR request of a particular function, the control unit may cause the associated application availability register to indicate that the application hardware within the particular function is not available to the driver. The control unit may reset the corresponding configuration space registers within a predetermined amount of time and reset the associated application hardware resources.

摘要翻译： I / O设备包括被配置为在指定的时间量内处理功能级别复位（FLR）请求的主机接口。 主机接口包括一个控制单元和一组配置空间寄存器，每个组对应一个功能。 主机接口还包括应用可用性寄存器，每个与相应功能相关联，并且其可以指示相应功能内的应用硬件是否可用于相应的应用设备驱动程序的访问。 I / O设备还包括与相应功能相关联的应用硬件资源。 响应于接收到特定功能的FLR请求，控制单元可以使相关联的应用可用性寄存器指示特定功能内的应用硬件对于驱动程序是不可用的。 控制单元可以在预定的时间量内重置相应的配置空间寄存器，并重置相关联的应用硬件资源。

公开(公告)号：US08312187B2

公开(公告)日：2012-11-13

申请号：US12562319

申请日：2009-09-18

申请人： Elisa Rodrigues ,  John E. Watkins

发明人： Elisa Rodrigues ,  John E. Watkins

IPC分类号： G06F13/00 ,  G06F5/00 ,  G06F3/00

CPC分类号： G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808

摘要： An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.

摘要翻译： I / O设备包括耦合到多个硬件资源的主机接口。 主机接口包括可以接收和处理由多个处理单元发送的多个事务层分组的事务层分组（TLP）处理单元。 每个处理单元可以对应于相应的根复合体。 TLP处理单元可以识别与每个事务层分组对应的事务类型和处理单元，并且根据事务类型和处理单元将每个事务层分组存储在存储器内。 TLP处理单元可以基于使用仲裁方案的一组公平标准从存储器中选择一个或多个事务层分组来进行进程调度。 TLP处理单元还可以基于附加标准进一步选择和调度事务层分组以供下游应用硬件处理。

公开(公告)号：US08286027B2

公开(公告)日：2012-10-09

申请号：US12787001

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

发明人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

IPC分类号： G06F11/00

CPC分类号： G06F11/0745 ,  G06F11/0724 ,  G06F11/0766

摘要： An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.

摘要翻译： I / O设备包括可以接收和处理由多个处理单元发送的事务分组的主机接口，每个处理单元对应于相应的根复合体。 主机接口包括具有在硬件中实现的错误逻辑的错误处理单元，其可以在接收到每个分组时确定每个事务分组是否具有错误并存储与任何检测到的错误相对应的信息。 错误处理单元可以包括错误处理器，其可被配置为执行错误处理指令以基于该信息来确定任何错误处理操作。 错误处理器还可以生成和发送一个或多个指令操作，每个指令操作对应于特定的错误处理操作。 错误处理单元还可以包括可以执行一个或多个指令操作以执行特定错误处理操作的错误处理单元。