公开(公告)号：US08402320B2

公开(公告)日：2013-03-19

申请号：US12786988

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F11/00

CPC分类号： G06F11/0766 ,  G06F11/0724 ,  G06F11/0745

摘要： An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may be configured to determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage. More particularly, the error handling unit may perform the error detection and capture of the error information as the transaction packets are received, or in real time, while the error handling unit may include firmware that may subsequently process the information corresponding to the detected errors.

摘要翻译： I / O设备包括主机接口，其可以被配置为接收和处理由多个处理单元发送的多个事务分组，每个处理单元对应于相应的根复合体。 主机接口包括错误处理单元，其具有在硬件中实现的错误逻辑，其可被配置为确定每个事务包是否具有错误并存储与存储器内的任何检测到的错误相对应的信息。 更具体地，错误处理单元可以在事件包被接收或实时地执行错误检测和捕获错误信息，而错误处理单元可以包括可以随后处理与检测到的错误相对应的信息的固件。

公开(公告)号：US08117350B2

公开(公告)日：2012-02-14

申请号：US12611694

申请日：2009-11-03

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F3/00

CPC分类号： G06F13/4221

摘要： The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region.

摘要翻译： 所描述的实施例提供用于访问配置空间寄存器（CSR）的值的系统。 该系统包括具有地址输入和CSR数据输出的CSR数据存储机制。 CSR数据存储机制包括存储多个存储器位置的存储器，用于存储针对相应设备的功能的CSR的真实值或实际值。 在这些实施例中，存储器位置被划分为至少一个共享区域和至少一个唯一区域。 在这些实施例中，响应于接收地址输入上的存储器位置的地址，CSR数据存储机构访问对应共享区域或唯一区域中的存储器位置中的CSR值。

公开(公告)号：US20110296255A1

公开(公告)日：2011-12-01

申请号：US12786988

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F11/07

CPC分类号： G06F11/0766 ,  G06F11/0724 ,  G06F11/0745

摘要： An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may be configured to determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage. More particularly, the error handling unit may perform the error detection and capture of the error information as the transaction packets are received, or in real time, while the error handling unit may include firmware that may subsequently process the information corresponding to the detected errors.

摘要翻译： I / O设备包括主机接口，其可以被配置为接收和处理由多个处理单元发送的多个事务分组，每个处理单元对应于相应的根复合体。 主机接口包括错误处理单元，其具有在硬件中实现的错误逻辑，其可被配置为确定每个事务包是否具有错误并存储与存储器内的任何检测到的错误相对应的信息。 更具体地，错误处理单元可以在事件包被接收或实时地执行错误检测和捕获错误信息，而错误处理单元可以包括可以随后处理与检测到的错误相对应的信息的固件。

公开(公告)号：US20110296256A1

公开(公告)日：2011-12-01

申请号：US12787001

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

发明人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

IPC分类号： G06F11/07

CPC分类号： G06F11/0745 ,  G06F11/0724 ,  G06F11/0766

摘要： An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.

摘要翻译： I / O设备包括可以接收和处理由多个处理单元发送的事务分组的主机接口，每个处理单元对应于相应的根复合体。 主机接口包括具有在硬件中实现的错误逻辑的错误处理单元，其可以在接收到每个分组时确定每个事务分组是否具有错误并存储与任何检测到的错误相对应的信息。 错误处理单元可以包括错误处理器，其可被配置为执行错误处理指令以基于该信息来确定任何错误处理操作。 错误处理器还可以生成和发送一个或多个指令操作，每个指令操作对应于特定的错误处理操作。 错误处理单元还可以包括可以执行一个或多个指令操作以执行特定错误处理操作的错误处理单元。

公开(公告)号：US20110106981A1

公开(公告)日：2011-05-05

申请号：US12611694

申请日：2009-11-03

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F3/00

CPC分类号： G06F13/4221

摘要： The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region.

摘要翻译： 所描述的实施例提供用于访问配置空间寄存器（CSR）的值的系统。 该系统包括具有地址输入和CSR数据输出的CSR数据存储机制。 CSR数据存储机制包括存储多个存储器位置的存储器，用于存储针对相应设备的功能的CSR的真实值或实际值。 在这些实施例中，存储器位置被划分为至少一个共享区域和至少一个唯一区域。 在这些实施例中，响应于接收地址输入上的存储器位置的地址，CSR数据存储机构访问对应共享区域或唯一区域中的存储器位置中的CSR值。

公开(公告)号：US20110072172A1

公开(公告)日：2011-03-24

申请号：US12562319

申请日：2009-09-18

申请人： Elisa Rodrigues ,  John E. Watkins

发明人： Elisa Rodrigues ,  John E. Watkins

IPC分类号： G06F13/14 ,  G06F3/00

CPC分类号： G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808

摘要： An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.

摘要翻译： I / O设备包括耦合到多个硬件资源的主机接口。 主机接口包括可以接收和处理由多个处理单元发送的多个事务层分组的事务层分组（TLP）处理单元。 每个处理单元可以对应于相应的根复合体。 TLP处理单元可以识别与每个事务层分组对应的事务类型和处理单元，并且根据事务类型和处理单元将每个事务层分组存储在存储器内。 TLP处理单元可以基于使用仲裁方案的一组公平标准从存储器中选择一个或多个事务层分组来进行进程调度。 TLP处理单元还可以基于附加标准进一步选择和调度事务层分组以供下游应用硬件处理。

公开(公告)号：US08527745B2

公开(公告)日：2013-09-03

申请号：US12632415

申请日：2009-12-07

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F15/177 ,  G06F9/00 ,  G06F11/00

CPC分类号： G06F13/102

摘要： An I/O device includes a host interface configured to process function level reset (FLR) requests in a specified amount of time. The host interface includes a control unit and groups of configuration space registers, each group corresponding to a function. The host interface also includes application availability registers, each associated with a respective function, and which may indicate whether application hardware within the respective function is available for access by a corresponding application device driver. The I/O device also includes application hardware resources associated with a respective function. In response to receiving an FLR request of a particular function, the control unit may cause the associated application availability register to indicate that the application hardware within the particular function is not available to the driver. The control unit may reset the corresponding configuration space registers within a predetermined amount of time and reset the associated application hardware resources.

摘要翻译： I / O设备包括被配置为在指定的时间量内处理功能级别复位（FLR）请求的主机接口。 主机接口包括一个控制单元和一组配置空间寄存器，每个组对应一个功能。 主机接口还包括应用可用性寄存器，每个与相应功能相关联，并且其可以指示相应功能内的应用硬件是否可用于相应的应用设备驱动程序的访问。 I / O设备还包括与相应功能相关联的应用硬件资源。 响应于接收到特定功能的FLR请求，控制单元可以使相关联的应用可用性寄存器指示特定功能内的应用硬件对于驱动程序是不可用的。 控制单元可以在预定的时间量内重置相应的配置空间寄存器，并重置相关联的应用硬件资源。

公开(公告)号：US08312187B2

公开(公告)日：2012-11-13

申请号：US12562319

申请日：2009-09-18

申请人： Elisa Rodrigues ,  John E. Watkins

发明人： Elisa Rodrigues ,  John E. Watkins

IPC分类号： G06F13/00 ,  G06F5/00 ,  G06F3/00

CPC分类号： G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808

摘要： An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.

摘要翻译： I / O设备包括耦合到多个硬件资源的主机接口。 主机接口包括可以接收和处理由多个处理单元发送的多个事务层分组的事务层分组（TLP）处理单元。 每个处理单元可以对应于相应的根复合体。 TLP处理单元可以识别与每个事务层分组对应的事务类型和处理单元，并且根据事务类型和处理单元将每个事务层分组存储在存储器内。 TLP处理单元可以基于使用仲裁方案的一组公平标准从存储器中选择一个或多个事务层分组来进行进程调度。 TLP处理单元还可以基于附加标准进一步选择和调度事务层分组以供下游应用硬件处理。

公开(公告)号：US08286027B2

公开(公告)日：2012-10-09

申请号：US12787001

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

发明人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

IPC分类号： G06F11/00

CPC分类号： G06F11/0745 ,  G06F11/0724 ,  G06F11/0766

摘要： An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.

摘要翻译： I / O设备包括可以接收和处理由多个处理单元发送的事务分组的主机接口，每个处理单元对应于相应的根复合体。 主机接口包括具有在硬件中实现的错误逻辑的错误处理单元，其可以在接收到每个分组时确定每个事务分组是否具有错误并存储与任何检测到的错误相对应的信息。 错误处理单元可以包括错误处理器，其可被配置为执行错误处理指令以基于该信息来确定任何错误处理操作。 错误处理器还可以生成和发送一个或多个指令操作，每个指令操作对应于特定的错误处理操作。 错误处理单元还可以包括可以执行一个或多个指令操作以执行特定错误处理操作的错误处理单元。

公开(公告)号：US20110138161A1

公开(公告)日：2011-06-09

申请号：US12632415

申请日：2009-12-07

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F9/00

CPC分类号： G06F13/102

摘要： An I/O device includes a host interface configured to process function level reset (FLR) requests in a specified amount of time. The host interface includes a control unit and groups of configuration space registers, each group corresponding to a function. The host interface also includes application availability registers, each associated with a respective function, and which may indicate whether application hardware within the respective function is available for access by a corresponding application device driver. The I/O device also includes application hardware resources associated with a respective function. In response to receiving an FLR request of a particular function, the control unit may cause the associated application availability register to indicate that the application hardware within the particular function is not available to the driver. The control unit may reset the corresponding configuration space registers within a predetermined amount of time and reset the associated application hardware resources.

摘要翻译： I / O设备包括被配置为在指定的时间量内处理功能级别复位（FLR）请求的主机接口。 主机接口包括一个控制单元和一组配置空间寄存器，每个组对应一个功能。 主机接口还包括应用可用性寄存器，每个与相应功能相关联，并且其可以指示相应功能内的应用硬件是否可用于相应的应用设备驱动程序的访问。 I / O设备还包括与相应功能相关联的应用硬件资源。 响应于接收到特定功能的FLR请求，控制单元可以使相关联的应用可用性寄存器指示特定功能内的应用硬件对于驱动程序是不可用的。 控制单元可以在预定的时间量内重置相应的配置空间寄存器，并重置相关联的应用硬件资源。