公开(公告)号：US20090187679A1

公开(公告)日：2009-07-23

申请号：US12017039

申请日：2008-01-20

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Elisa Rodrigues

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Elisa Rodrigues

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A universal DMA (Direct Memory Access) engine can be dynamically configured to function in either a receive or transmit mode. DMAs are logically assembled and bound as needed, without limitation to a fixed, pre-determined number of receive engines and transmit engines. Because a DMA engine may be dynamically assembled to support the flow of data in either direction, varied usage models are enabled, and components used to assemble a receive DMA engine for one application may be subsequently used to assemble a transmit engine for a different application. An application may request a specific number of each type of engine, depending on the nature of its input/output traffic. The number of receive or transmit engines can be dynamically increased or decreased without suspending or rebooting the host. A universal DMA architecture provides a unified software framework, thereby decreasing the complexity of the software and the hardware gate count cost.

摘要翻译： 通用DMA（直接存储器访问）引擎可以动态配置为以接收或发送模式工作。 根据需要，逻辑上组装和绑定DMA，而不限于固定的预定数量的接收引擎和传输引擎。 因为可以动态地组装DMA引擎以支持任一方向上的数据流，所以可以使用各种使用模型，并且用于组合一个应用的接收DMA引擎的组件可以随后用于组装用于不同应用的传输引擎。 应用可以根据其输入/输出流量的性质来请求每种类型的引擎的特定数量。 接收或发送引擎的数量可以动态增加或减少，而不会挂起或重新启动主机。 通用DMA架构提供统一的软件框架，从而降低软件的复杂性和硬件门数的成本。

公开(公告)号：US06985153B2

公开(公告)日：2006-01-10

申请号：US10195861

申请日：2002-07-15

申请人： Elisa Rodrigues ,  Lisa C. Grenier ,  Nimita J. Taneja

发明人： Elisa Rodrigues ,  Lisa C. Grenier ,  Nimita J. Taneja

IPC分类号： G06F13/18

CPC分类号： G06T1/00

摘要： A graphics system comprising a scheduling network, a sample buffer and a plurality of filtering units. The sample buffer is configured to store sample generated by a rendering engine. The plurality of filtering units are coupled in a linear series. Each filtering unit of the linear series is configured to send a request for a scanline of sample bins to a first filtering unit of the linear series. The first filtering unit is configured to service the scanline requests by sending burst requests to a scheduling network and coordinating the flow of samples forming the bursts from the sample buffer to the filtering units.

摘要翻译： 一种包括调度网络，采样缓冲器和多个滤波单元的图形系统。 样本缓冲区被配置为存储由渲染引擎生成的样本。 多个滤波单元以线性系列耦合。 线性系列的每个滤波单元被配置为向线性序列的第一滤波单元发送对样本仓的扫描线的请求。 第一过滤单元被配置为通过向调度网络发送突发请求来服务扫描线请求，并且协调从采样缓冲器到滤波单元的形成脉冲串的样本流。

公开(公告)号：US20110296256A1

公开(公告)日：2011-12-01

申请号：US12787001

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

发明人： John E. Watkins ,  Elisa Rodrigues ,  Abbas Morshed

IPC分类号： G06F11/07

CPC分类号： G06F11/0745 ,  G06F11/0724 ,  G06F11/0766

摘要： An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.

摘要翻译： I / O设备包括可以接收和处理由多个处理单元发送的事务分组的主机接口，每个处理单元对应于相应的根复合体。 主机接口包括具有在硬件中实现的错误逻辑的错误处理单元，其可以在接收到每个分组时确定每个事务分组是否具有错误并存储与任何检测到的错误相对应的信息。 错误处理单元可以包括错误处理器，其可被配置为执行错误处理指令以基于该信息来确定任何错误处理操作。 错误处理器还可以生成和发送一个或多个指令操作，每个指令操作对应于特定的错误处理操作。 错误处理单元还可以包括可以执行一个或多个指令操作以执行特定错误处理操作的错误处理单元。

公开(公告)号：US20110106981A1

公开(公告)日：2011-05-05

申请号：US12611694

申请日：2009-11-03

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F3/00

CPC分类号： G06F13/4221

摘要： The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region.

摘要翻译： 所描述的实施例提供用于访问配置空间寄存器（CSR）的值的系统。 该系统包括具有地址输入和CSR数据输出的CSR数据存储机制。 CSR数据存储机制包括存储多个存储器位置的存储器，用于存储针对相应设备的功能的CSR的真实值或实际值。 在这些实施例中，存储器位置被划分为至少一个共享区域和至少一个唯一区域。 在这些实施例中，响应于接收地址输入上的存储器位置的地址，CSR数据存储机构访问对应共享区域或唯一区域中的存储器位置中的CSR值。

公开(公告)号：US20110072172A1

公开(公告)日：2011-03-24

申请号：US12562319

申请日：2009-09-18

申请人： Elisa Rodrigues ,  John E. Watkins

发明人： Elisa Rodrigues ,  John E. Watkins

IPC分类号： G06F13/14 ,  G06F3/00

CPC分类号： G06F13/385 ,  G06F2213/0026 ,  G06F2213/3808

摘要： An I/O device includes a host interface coupled to a plurality of hardware resources. The host interface includes a transaction layer packet (TLP) processing unit that may receive and process a plurality of transaction layer packets sent by a plurality of processing units. Each processing unit may correspond to a respective root complex. The TLP processing unit may identify a transaction type and a processing unit corresponding to each transaction layer packet and store each transaction layer packet within a storage according to the transaction type and the processing unit. The TLP processing unit may select one or more transaction layer packets from the storage for process scheduling based upon a set of fairness criteria using an arbitration scheme. The TLP processing unit may further select and dispatch transaction layer packets for processing by downstream application hardware based upon additional criteria.

摘要翻译： I / O设备包括耦合到多个硬件资源的主机接口。 主机接口包括可以接收和处理由多个处理单元发送的多个事务层分组的事务层分组（TLP）处理单元。 每个处理单元可以对应于相应的根复合体。 TLP处理单元可以识别与每个事务层分组对应的事务类型和处理单元，并且根据事务类型和处理单元将每个事务层分组存储在存储器内。 TLP处理单元可以基于使用仲裁方案的一组公平标准从存储器中选择一个或多个事务层分组来进行进程调度。 TLP处理单元还可以基于附加标准进一步选择和调度事务层分组以供下游应用硬件处理。

公开(公告)号：US07620693B1

公开(公告)日：2009-11-17

申请号：US10811557

申请日：2004-03-29

申请人： James A. Mott ,  Elisa Rodrigues

发明人： James A. Mott ,  Elisa Rodrigues

IPC分类号： G06F15/167 ,  G06F13/18

CPC分类号： H04L49/9047 ,  H04L47/621 ,  H04L49/90 ,  H04L49/901 ,  H04L69/08 ,  H04L69/324

摘要： A system and method for tracking responses to InfiniBand RDMA Reads. When an RDMA Read or Read request is issued by a transmit module, a receive module is informed of the packet sequence numbers (PSN) associated with the expected RDMA Read responses. The receive module maintains a linked list for each queue pair that issues RDMA Reads. Each entry in the linked list corresponds to one RDMA Read for the associated queue pair, and identifies the first and last PSN and includes a link to the next entry in the linked list. When the final RDMA Read response is received, the receive module notifies the transmit module, which can then retire the RDMA Read from its retry queue.

摘要翻译： 跟踪InfiniBand RDMA读取响应的系统和方法。 当发送模块发出RDMA读取或读取请求时，通知接收模块与预期RDMA读取响应相关联的数据包序列号（PSN）。 接收模块维护发出RDMA读取的每个队列对的链表。 链表中的每个条目对应于相关联的队列对的一个RDMA读取，并且识别第一个和最后一个PSN，并且包括链接到链表中的下一个条目。 当接收到最终的RDMA读取响应时，接收模块通知发送模块，然后发送模块可以从其重试队列中退出RDMA读取。

公开(公告)号：US08402320B2

公开(公告)日：2013-03-19

申请号：US12786988

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F11/00

CPC分类号： G06F11/0766 ,  G06F11/0724 ,  G06F11/0745

摘要： An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may be configured to determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage. More particularly, the error handling unit may perform the error detection and capture of the error information as the transaction packets are received, or in real time, while the error handling unit may include firmware that may subsequently process the information corresponding to the detected errors.

摘要翻译： I / O设备包括主机接口，其可以被配置为接收和处理由多个处理单元发送的多个事务分组，每个处理单元对应于相应的根复合体。 主机接口包括错误处理单元，其具有在硬件中实现的错误逻辑，其可被配置为确定每个事务包是否具有错误并存储与存储器内的任何检测到的错误相对应的信息。 更具体地，错误处理单元可以在事件包被接收或实时地执行错误检测和捕获错误信息，而错误处理单元可以包括可以随后处理与检测到的错误相对应的信息的固件。

公开(公告)号：US08117350B2

公开(公告)日：2012-02-14

申请号：US12611694

申请日：2009-11-03

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F3/00

CPC分类号： G06F13/4221

摘要： The described embodiments provide a system for accessing values for configuration space registers (CSRs). This system includes a CSR data storage mechanism with an address input and a CSR data output. The CSR data storage mechanism includes a memory containing a number of memory locations for storing the true or actual values for CSRs for functions for corresponding devices. In these embodiments, the memory locations are divided into at least one shared region and at least one unique region. In these embodiments, in response to receiving an address for a memory location on the address input, the CSR data storage mechanism accesses the value for the CSR in the memory location in a corresponding shared region or unique region.

摘要翻译： 所描述的实施例提供用于访问配置空间寄存器（CSR）的值的系统。 该系统包括具有地址输入和CSR数据输出的CSR数据存储机制。 CSR数据存储机制包括存储多个存储器位置的存储器，用于存储针对相应设备的功能的CSR的真实值或实际值。 在这些实施例中，存储器位置被划分为至少一个共享区域和至少一个唯一区域。 在这些实施例中，响应于接收地址输入上的存储器位置的地址，CSR数据存储机构访问对应共享区域或唯一区域中的存储器位置中的CSR值。

公开(公告)号：US20110296255A1

公开(公告)日：2011-12-01

申请号：US12786988

申请日：2010-05-25

申请人： John E. Watkins ,  Elisa Rodrigues

发明人： John E. Watkins ,  Elisa Rodrigues

IPC分类号： G06F11/07

CPC分类号： G06F11/0766 ,  G06F11/0724 ,  G06F11/0745

摘要： An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may be configured to determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage. More particularly, the error handling unit may perform the error detection and capture of the error information as the transaction packets are received, or in real time, while the error handling unit may include firmware that may subsequently process the information corresponding to the detected errors.

摘要翻译： I / O设备包括主机接口，其可以被配置为接收和处理由多个处理单元发送的多个事务分组，每个处理单元对应于相应的根复合体。 主机接口包括错误处理单元，其具有在硬件中实现的错误逻辑，其可被配置为确定每个事务包是否具有错误并存储与存储器内的任何检测到的错误相对应的信息。 更具体地，错误处理单元可以在事件包被接收或实时地执行错误检测和捕获错误信息，而错误处理单元可以包括可以随后处理与检测到的错误相对应的信息的固件。

公开(公告)号：US08032669B2

公开(公告)日：2011-10-04

申请号：US12017039

申请日：2008-01-20

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Elisa Rodrigues

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Elisa Rodrigues

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A universal DMA (Direct Memory Access) engine can be dynamically configured to function in either a receive or transmit mode. DMAs are logically assembled and bound as needed, without limitation to a fixed, pre-determined number of receive engines and transmit engines. Because a DMA engine may be dynamically assembled to support the flow of data in either direction, varied usage models are enabled, and components used to assemble a receive DMA engine for one application may be subsequently used to assemble a transmit engine for a different application. An application may request a specific number of each type of engine, depending on the nature of its input/output traffic. The number of receive or transmit engines can be dynamically increased or decreased without suspending or rebooting the host. A universal DMA architecture provides a unified software framework, thereby decreasing the complexity of the software and the hardware gate count cost.

摘要翻译： 通用DMA（直接存储器访问）引擎可以动态配置为以接收或发送模式工作。 根据需要，逻辑上组装和绑定DMA，而不限于固定的预定数量的接收引擎和传输引擎。 因为可以动态地组装DMA引擎以支持任一方向上的数据流，所以可以使用各种使用模型，并且用于组合一个应用的接收DMA引擎的组件可以随后用于组装用于不同应用的传输引擎。 应用可以根据其输入/输出流量的性质来请求每种类型的引擎的特定数量。 接收或发送引擎的数量可以动态增加或减少，而不会挂起或重新启动主机。 通用DMA架构提供统一的软件框架，从而降低软件的复杂性和硬件门数的成本。