公开(公告)号：US20090015397A1

公开(公告)日：2009-01-15

申请号：US12170800

申请日：2008-07-10

申请人： DAVID J. EARDLEY ,  NORBERT J. TOBBE ,  JOHN E. WATKINS

发明人： DAVID J. EARDLEY ,  NORBERT J. TOBBE ,  JOHN E. WATKINS

IPC分类号： H04Q7/00 ,  H04M11/04

CPC分类号： H04M11/04

摘要： An emergency communication device is disclosed herein, including a substantially enclosed housing, at least one receiver, at least one transformer, at least one latching relay, at least one power supply, wherein the receiver, transformer, latching relay, and power supply are located within the housing, a telephone cord, an automatic dialer, wherein the automatic dialer is operatively connected to the housing, and is operatively connected to at least the power supply, and a flashing light.

摘要翻译： 本文公开了一种紧急通信装置，包括基本封闭的壳体，至少一个接收器，至少一个变压器，至少一个闭锁继电器，至少一个电源，其中所述接收器，变压器，闭锁继电器和电源位于 在壳体内，电话线，自动拨号器，其中自动拨号器可操作地连接到外壳，并且可操作地连接到至少电源和闪光灯。

公开(公告)号：US06453360B1

公开(公告)日：2002-09-17

申请号：US09259765

申请日：1999-03-01

申请人： Shimon Muller ,  Denton E. Gentry, Jr. ,  John E. Watkins ,  Linda T. Cheng

发明人： Shimon Muller ,  Denton E. Gentry, Jr. ,  John E. Watkins ,  Linda T. Cheng

IPC分类号： G06F1300

CPC分类号： H04L49/9094 ,  H04L29/06 ,  H04L47/2441 ,  H04L49/90 ,  H04L49/9042 ,  H04L49/9063 ,  H04L49/9078 ,  H04L69/16 ,  H04L69/161 ,  H04L69/167 ,  H04L69/18 ,  H04L69/22 ,  H04L69/26

摘要： A high performance network interface is provided for receiving a packet from a network and transferring it to a host computer system. A header portion of a received packet is parsed by a parser module to determine the packet's compatibility with, or conformance to, one or more pre-selected protocols. If compatible, a number of processing functions may be performed to increase the efficiency with which the packet is handled. In one function, a re-assembly engine re-assembles, in a re-assembly buffer, data portions of multiple packets in a single communication flow or connection. Header portions of such packets are stored in a header buffer. An incompatible packet may be stored in another buffer. In another function, a packet batching module determines when multiple packets in one flow are transferred to the host computer system, so that their header portions are processed collectively rather than being interspersed with headers of other flows' packets. In yet another function, the processing of packets through their protocol stacks is distributed among multiple processors by a load distributor, based on their communication flows. A flow database is maintained by a flow database manager to reflect the creation, termination and activity of flows. A packet queue stores packets to await transfer to the host computer system, and a control queue stores information concerning the waiting packets. If the packet queue becomes saturated with packets, a random packet may be discarded. An interrupt modulator may modulate the rate at which interrupts associated with packet arrival events are issued to the host computer system.

摘要翻译： 提供了一种高性能网络接口，用于从网络接收分组并将其传送到主机系统。 接收到的分组的报头部分由解析器模块解析以确定分组与一个或多个预选协议的兼容性或符合一个或多个预选协议。 如果兼容，则可以执行多个处理功能以提高处理分组的效率。 在一个功能中，重新组装引擎在重新组装缓冲器中重新组装单个通信流或连接中的多个分组的数据部分。 这些分组的报头部分被存储在报头缓冲器中。 不兼容的数据包可能存储在另一个缓冲区中。 在另一个功能中，分组批处理模块确定一个流中的多个分组何时被传送到主计算机系统，使得它们的头部部分被集体处理，而不是散布在其他流的分组的头部。 在另一个功能中，通过它们的协议栈对分组的处理由负载分配器基于它们的通信流分布在多个处理器之间。 流数据库由流数据库管理器维护，以反映流的创建，终止和活动。 分组队列存储分组以等待传送到主计算机系统，并且控制队列存储关于等待分组的信息。 如果分组队列变得饱和，则随机分组可能被丢弃。 中断调制器可以调制与主机计算机系统发出与分组到达事件相关联的中断的速率。

公开(公告)号：US5854911A

公开(公告)日：1998-12-29

申请号：US675263

申请日：1996-07-01

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F13/00 ,  G06F9/38 ,  H04L12/56 ,  H04Q11/04 ,  G06F13/12 ,  G06F13/14

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5681

摘要： A prefetch apparatus optimizes bandwidth in a computer network by prefetch accessing data blocks prior to their demand in an ATM network thereby effectively reducing memory read latency. The method of the preferred embodiment includes the steps of: 1) computing a prefetch address of a next sequential data block given an address of a requested data block; 2) comparing a current request address against a previously computed prefetch address; and 3) generating a hit/miss indication corresponding to whether the current request address matches the previously computed prefetch address.

摘要翻译： 预取装置通过在ATM网络中的需求之前预取访问数据块来优化计算机网络中的带宽，从而有效地减少存储器读取延迟。 优选实施例的方法包括以下步骤：1）计算给定所请求数据块的地址的下一个顺序数据块的预取地址; 2）将当前请求地址与先前计算的预取地址进行比较; 以及3）产生与当前请求地址是否匹配先前计算的预取地址相对应的命中/未命中指示。

公开(公告)号：US4055935A

公开(公告)日：1977-11-01

申请号：US655866

申请日：1976-02-06

申请人： William R. Malion ,  John E. Watkins

发明人： William R. Malion ,  John E. Watkins

IPC分类号： A01D34/68 ,  F16D67/02 ,  A01D75/18 ,  A01D69/10 ,  H02G11/00

CPC分类号： A01D34/6812 ,  F16D67/02 ,  A01D2101/00

摘要： A lawnmower has an improved clutch-brake mechanism interposed between the engine drive shaft and the rotating blade to stop the blade except when an operator tensions a control cable. The clutch-brake includes cylindrical input and output members selectively drivingly coupled by a clutch spring wound around both members. A control sleeve positioned around the clutch spring connects with the input end of the clutch spring. When the control sleeve is braked, the clutch spring releases its grip on the input member and the output is no longer driven. A coiled brake band extends around the control sleeve to selectively effect this braking action. An improved floating mount is provided for the brake band. An improved lost-motion connection is provided between the control sleeve and the output member to limit the twisting of the clutch spring. An optional slip clutch is provided for connecting the output member to the blade.

摘要翻译： 割草机具有改进的离合器制动机构，其插入在发动机驱动轴和旋转叶片之间，以便除了当操作者拉紧控制缆索之后停止叶片。 离合器制动器包括通过缠绕在两个构件上的离合器弹簧选择性地驱动联接的圆柱形输入和输出构件。 定位在离合器弹簧周围的控制套筒与离合器弹簧的输入端连接。 当控制套筒被制动时，离合器弹簧释放其对输入构件的夹紧，并且输出不再被驱动。 线圈制动带围绕控制套筒延伸以选择性地实现该制动动作。 为制动带提供改进的浮动安装。 在控制套筒和输出构件之间提供改进的空动连接以限制离合器弹簧的扭转。 提供了可选的滑动离合器用于将输出构件连接到叶片。

公开(公告)号：US3530683A

公开(公告)日：1970-09-29

申请号：US3530683D

申请日：1969-04-16

申请人： JOHN E WATKINS

发明人： WATKINS JOHN E

IPC分类号： F25D13/06 ,  F25D17/04 ,  F25D17/06

CPC分类号： F25D17/06 ,  F25D13/067 ,  F25D17/04

公开(公告)号：US08176304B2

公开(公告)日：2012-05-08

申请号：US12256250

申请日：2008-10-22

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Louise Y. Yeung ,  Marcelino M. Dignum ,  John E. Watkins

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Louise Y. Yeung ,  Marcelino M. Dignum ,  John E. Watkins

IPC分类号： G06F9/00 ,  G06F15/177 ,  G06F1/24 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F13/385

摘要： An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.

摘要翻译： 具有功能级复位功能的I / O设备包括主机接口，其可以包括主复位单元，多个客户端接口，每个对应于一个或多个功能，以及多个硬件资源。 每个硬件资源可以与相应的功能相关联。 响应于接收到重置特定功能的复位请求，主复位单元可以向每个客户端接口提供对应于重置请求的请求信号，以及标识特定功能的信号。 具有与特定功能的关联的每个客户端接口可以启动相关联的硬件资源的复位操作，并且响应于硬件资源的复位操作的完成，向主复位单元提供用于特定功能的客户端重置完成信号 。 主复位单元为主机接口提供特定功能的复位完成信号。

公开(公告)号：US20100100717A1

公开(公告)日：2010-04-22

申请号：US12256250

申请日：2008-10-22

申请人： Rahoul Puri ,  Arvind Srinivasan ,  Louise Y. Yeung ,  Marcelino M. Dignum ,  John E. Watkins

发明人： Rahoul Puri ,  Arvind Srinivasan ,  Louise Y. Yeung ,  Marcelino M. Dignum ,  John E. Watkins

IPC分类号： G06F9/00

CPC分类号： G06F13/385

摘要： An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface.

摘要翻译： 具有功能级复位功能的I / O设备包括主机接口，其可以包括主复位单元，多个客户端接口，每个对应于一个或多个功能，以及多个硬件资源。 每个硬件资源可以与相应的功能相关联。 响应于接收到重置特定功能的复位请求，主复位单元可以向每个客户端接口提供对应于重置请求的请求信号，以及标识特定功能的信号。 具有与特定功能的关联的每个客户端接口可以启动相关联的硬件资源的复位操作，并且响应于硬件资源的复位操作的完成，向主复位单元提供用于特定功能的客户端重置完成信号 。 主复位单元为主机接口提供特定功能的复位完成信号。

公开(公告)号：US20090307702A1

公开(公告)日：2009-12-10

申请号：US12135356

申请日：2008-06-09

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F9/46 ,  G06F9/44

CPC分类号： G06F13/12 ,  G06F12/1441

摘要： A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes a storage for storing a resource discovery table, and programmed I/O (PIO) configuration registers corresponding to hardware resources. A system processor may allocate the plurality of hardware resources to one or more functions, and to populate each entry of the resource discovery table for each function. The processing units may execute one or more processes. Given processing units may further execute OS instructions to allocate space for an I/O mapping of a PIO configuration space in a system memory, and to assign a function to a respective process. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

摘要翻译： 系统包括耦合到一个或多个处理单元的虚拟化I / O设备。 虚拟化I / O设备包括用于存储资源发现表的存储器和对应于硬件资源的编程I / O（PIO）配置寄存器。 系统处理器可以将多个硬件资源分配给一个或多个功能，并且为每个功能填充资源发现表的每个条目。 处理单元可以执行一个或多个处理。 给定的处理单元可以进一步执行OS指令以为系统存储器中的PIO配置空间的I / O映射分配空间，并且将功能分配给相应的进程。 处理单元可以执行与给定进程相关联的设备驱动器实例，以通过请求对资源发现表的访问来发现分配的资源。 虚拟化I / O设备通过检查对资源发现表的访问请求来保护资源。

公开(公告)号：US06480489B1

公开(公告)日：2002-11-12

申请号：US09260333

申请日：1999-03-01

申请人： Shimon Muller ,  Denton E. Gentry, Jr. ,  Linda T. Cheng ,  John E. Watkins

发明人： Shimon Muller ,  Denton E. Gentry, Jr. ,  Linda T. Cheng ,  John E. Watkins

IPC分类号： H04L1228

CPC分类号： H04L49/9042 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9021 ,  H04L49/9068 ,  H04L49/9094

摘要： A system and method are provided for transferring a packet received from a network to a host computer according to an operation code associated with the packet. A packet received at a network interface is parsed to retrieve information from a header portion of the packet. A flow key is generated for a received packet that was formatted with one of a set of predetermined protocols. A packet's flow key identifies a communication flow that comprises the packet. Based on some of the retrieved information, a code is associated with the packet to inform a transfer engine how the packet should be transferred to host memory. Based on a packet's code, the transfer engine stores the packet in one or more host memory buffers. If the packet was formatted with one of the set of predetermined protocols, its data is re-assembled in a re-assembly buffer with data from other packets in the same communication flow. Re-assembled data may be provided to a destination application or user through page flipping. If the packet is being re-assembled, a header portion of the packet is stored in a separate header buffer. If the packet is not being re-assembled, it is stored in its entirety in the header buffer if it is smaller than a predetermined threshold. If a non-re-assembled packet is larger than the threshold for the header buffer, it is stored in another type of buffer for larger non-re-assembled packets. After a packet is stored in a buffer, the transfer engine informs the host computer of the packet by configuring a descriptor with information on the packet and releasing the descriptor to the host computer.

摘要翻译： 提供了一种系统和方法，用于根据与分组相关联的操作码将从网络接收到的分组传送到主计算机。 在网络接口处接收的分组被解析以从分组的报头部分检索信息。 针对以一组预定协议格式化的接收分组生成流密钥。 分组的流密钥标识包括分组的通信流。 基于一些检索到的信息，代码与分组相关联以通知传输引擎如何将分组传送到主机存储器。 基于分组的代码，传输引擎将分组存储在一个或多个主机存储器缓冲器中。 如果分组被格式化为预定协议集合中的一个，则其数据在具有来自相同通信流中的其他分组的数据的重新组装缓冲器中被重新组装。 可以通过翻页翻页将重新组装的数据提供给目的地应用程序或用户。 如果分组被重新组装，则分组的报头部分被存储在单独的报头缓冲器中。 如果分组未被重新组装，则如果分组小于预定阈值，则将其整体存储在报头缓冲器中。 如果非重新组合的分组大于报头缓冲区的阈值，则将其存储在另一种类型的缓冲器中用于较大的非重新组装的分组。 在将数据包存储在缓冲器中之后，传输引擎通过配置具有关于分组的信息的描述符并将该描述符释放到主机来通知主机计算机。

公开(公告)号：US6073224A

公开(公告)日：2000-06-06

申请号：US673050

申请日：1996-07-01

申请人： John E. Watkins

发明人： John E. Watkins

IPC分类号： G06F12/02 ,  G06F12/10 ,  G06F12/12 ,  H04Q3/00

CPC分类号： G06F12/126 ,  G06F12/1027 ,  G06F12/1081

摘要： A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a portion of the memory that can be invalidated by a lesser number of events than the unlocked region. In one embodiment, replacement circuitry of the address translation unit may invalidate address translations only stored in the unlocked region. The replacement circuitry comprises a counter to produce a first count value upon detecting that at least a first command has been issued to the address translation unit and each entry of the memory is currently in a valid state. Also, the replacement circuitry comprises an increment controller to control the counter to produce the first count value that addresses an entry of the memory within the second address range.

摘要翻译： 用于将地址转换单元内部的存储器的地址条目分离到锁定和解锁区域的电路和方法。 锁定区域是存储器的一部分，可以通过比未锁定区域少的事件使其无效。 在一个实施例中，地址转换单元的替换电路可以使仅存储在解锁区域中的地址转换失效。 替换电路包括计数器，用于在检测到至少第一命令已被发出到地址转换单元并且存储器的每个条目当前处于有效状态时产生第一计数值。 此外，替换电路包括增量控制器，用于控制计数器以产生寻址第二地址范围内的存储器条目的第一计数值。