公开(公告)号：US20230315637A1

公开(公告)日：2023-10-05

申请号：US17713263

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gregory William Alexander ,  Tu-An T. Nguyen ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  CHRISTIAN JACOBI

IPC: G06F12/084 ,  G06F12/0831 ,  G06F9/30 ,  G06F7/58

CPC classification number: G06F12/084 ,  G06F12/0833 ,  G06F9/30134 ,  G06F7/584

Abstract: A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

公开(公告)号：US20230315629A1

公开(公告)日：2023-10-05

申请号：US17713267

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Vesselina Papazova

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

公开(公告)号：US20230214218A1

公开(公告)日：2023-07-06

申请号：US17569951

申请日：2022-01-06

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Brian D. Barrick ,  Dung Q. Nguyen ,  Richard J. Eickemeyer ,  John B. Griswell, JR. ,  Balaram Sinharoy ,  Brian W. Thompto ,  Tu-An T. Nguyen

IPC: G06F9/30 ,  G06F9/38 ,  G06N5/04

CPC classification number: G06F9/30058 ,  G06F9/30043 ,  G06F9/30021 ,  G06F9/3855 ,  G06F9/3842 ,  G06N5/04

Abstract: A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

公开(公告)号：US10127121B2

公开(公告)日：2018-11-13

申请号：US15172248

申请日：2016-06-03

Applicant: International Business Machines Corporation

Inventor： Khandker N. Adeeb ,  Steven J. Battle ,  Brandon R. Goddard ,  Dung Q. Nguyen ,  Tu-An T. Nguyen ,  Nicholas R. Orzol ,  Brian D. Victor ,  Brendan M. Wong

IPC: G06F11/00 ,  G06F11/14

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and a plurality of load/store slices, where the load/store slices are coupled to the execution slices via a results bus. Operation of such a multi-slice processor includes: capturing first state information corresponding to a first set of control signals; monitoring state information of a plurality of logical components of the multi-slice processor; selecting, in dependence upon one or more selection criteria and upon the monitored state information, a second set of control signals; and capturing second state information corresponding to the second set of control signals, wherein the first set of control signals is different than the second set of control signals.

公开(公告)号：US11907125B2

公开(公告)日：2024-02-20

申请号：US17713263

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Gregory William Alexander ,  Tu-An T. Nguyen ,  Deanna Postles Dunn Berger ,  Timothy Bronson ,  Christian Jacobi

IPC: G06F12/084 ,  G06F7/58 ,  G06F9/30 ,  G06F12/0831

CPC classification number: G06F12/084 ,  G06F7/584 ,  G06F9/30134 ,  G06F12/0833

Abstract: A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

公开(公告)号：US11709676B2

公开(公告)日：2023-07-25

申请号：US17406186

申请日：2021-08-19

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Brian D. Barrick ,  Dung Q. Nguyen ,  Richard J. Eickemeyer ,  John B. Griswell, Jr. ,  Balaram Sinharoy ,  Brian W. Thompto ,  Tu-An T. Nguyen

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30021 ,  G06F9/3857 ,  G06F9/3861

Abstract: Aspects of the invention include includes determining a first instruction in a processing pipeline, wherein the first instruction includes a compare instruction, determining a second instruction in the processing pipeline, wherein the second instruction includes a conditional branch instruction relying on the compare instruction, determining a predicted result of the compare instruction, and completing the conditional branch instruction using the predicted result prior to executing the compare instruction.

公开(公告)号：US11269647B2

公开(公告)日：2022-03-08

申请号：US15845871

申请日：2017-12-18

Applicant: International Business Machines Corporation

Inventor： Kenneth L. Ward ,  Susan E. Eisen ,  Dung Q. Nguyen ,  Glenn O. Kincaid ,  Christopher M. Mueller ,  Tu-An T. Nguyen ,  Gaurav Mittal ,  Deepak K. Singh

IPC: G06F9/30 ,  G06F9/38

Abstract: A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

公开(公告)号：US20220066830A1

公开(公告)日：2022-03-03

申请号：US17004573

申请日：2020-08-27

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Dung Q. Nguyen ,  Albert J. Van Norstrand, JR. ,  Tu-An T. Nguyen ,  Cliff Kucharski

IPC: G06F9/50 ,  G06F16/178

Abstract: Disclosed is a method for rebalancing blocks of a register file. The method comprises allocating a first set of entries in a first register file to a first hardware thread of a processor core. The method further comprises allocating a second set of entries in a second register file to a second hardware thread of the processor core. The register tags in the first and second register files are compacted such that register tags associated with the first hardware thread are compacted into the first set of entries, and register tags associated with the second hardware thread are compacted into the second set of entries.

公开(公告)号：US20180217843A1

公开(公告)日：2018-08-02

申请号：US15939367

申请日：2018-03-29

Applicant: International Business Machines Corporation

Inventor： Salma Ayub ,  Jeffrey C. Brownscheidle ,  Sundeep Chadha ,  Dung Q. Nguyen ,  Tu-An T. Nguyen ,  Salim A. Shah ,  Brian W. Thompto

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3867 ,  G06F9/3887

Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

公开(公告)号：US12038841B2

公开(公告)日：2024-07-16

申请号：US17713264

申请日：2022-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tu-An T. Nguyen ,  Matthias Klein ,  Gregory William Alexander ,  Jason D. Kohl ,  Winston Herring ,  Timothy Bronson ,  Christian Jacobi

IPC: G06F12/08 ,  G06F9/34 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F9/34 ,  G06F9/3816 ,  G06F12/0815 ,  G06F12/0897

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.