公开(公告)号：US20200142702A1

公开(公告)日：2020-05-07

申请号：US16179245

申请日：2018-11-02

Applicant: International Business Machines Corporation

Inventor： Ehsan Fatehi ,  Richard J. Eickemeyer ,  Edmund J. Gieske

IPC: G06F9/38 ,  G06F9/30

Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.

公开(公告)号：US10175987B2

公开(公告)日：2019-01-08

申请号：US15072717

申请日：2016-03-17

Applicant: International Business Machines Corporation

Inventor： Richard J. Eickemeyer ,  Sheldon Levenstein ,  David S. Levitan ,  Mauricio J. Serrano

IPC: G06F9/38 ,  G06F9/32 ,  G06F12/0891 ,  G06F12/0875 ,  G06F12/0862 ,  G06F9/30

Abstract: Instruction prefetching in a computer processor includes, upon a miss in an instruction cache for an instruction cache line: retrieving, for the instruction cache line, a prefetch prediction vector, the prefetch prediction vector representing one or more cache lines of a set of contiguous instruction cache lines following the instruction cache line to prefetch from backing memory; and prefetching, from backing memory into the instruction cache, the instruction cache lines indicated by the prefetch prediction vector.

公开(公告)号：US11868773B2

公开(公告)日：2024-01-09

申请号：US17569951

申请日：2022-01-06

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Brian D. Barrick ,  Dung Q. Nguyen ,  Richard J. Eickemeyer ,  John B. Griswell, Jr. ,  Balaram Sinharoy ,  Brian W. Thompto ,  Tu-An T. Nguyen

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30021 ,  G06F9/30043 ,  G06F9/3842 ,  G06F9/3856

Abstract: A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

公开(公告)号：US10353710B2

公开(公告)日：2019-07-16

申请号：US15141112

申请日：2016-04-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard J. Eickemeyer ,  Naga P. Gorti ,  David S. Levitan ,  Albert J. Van Norstrand, Jr.

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875

Abstract: A technique for operating a processor includes identifying a difficult branch instruction (branch) whose target address (target) has been mispredicted multiple times. Information about the branch (which includes a current target and a next target) is learned and stored in a data structure. In response to the branch executing subsequent to the storing, whether a branch target of the branch corresponds to the current target in the data structure is determined. In response to the branch target of the branch corresponding to the current target of the branch in the data structure, the next target of the branch that is associated with the current target of the branch in the data structure is determined. In response to detecting that a next instance of the branch has been fetched, the next target of the branch is utilized as the predicted target for execution of the next instance of the branch.

公开(公告)号：US10191845B2

公开(公告)日：2019-01-29

申请号：US15606977

申请日：2017-05-26

Applicant: International Business Machines Corporation

Inventor： Bernard C. Drerup ,  Richard J. Eickemeyer ,  Guy L. Guthrie ,  Mohit Karve ,  George W. Rohrbaugh, III ,  Brian W. Thompto

IPC: G06F12/0862 ,  G06F12/0897

Abstract: Techniques are disclosed for identifying data streams in a processor that are likely to and not likely to benefit from data prefetching. A prefetcher receives at least a first request in a plurality of requests to pre-fetch data from a stream in a plurality of streams. The prefetcher assigns a confidence level to the first request based on an amount of confirmations observed in the stream. The request is in a confident state if the confidence level exceeds a specified value. The first request is in a non-confident state if the confidence level does not exceed the specified value. Requests to prefetch data in the plurality of requests that are associated with respective streams with a low prefetch utilization are deprioritized. Doing so allows a memory controller to determine whether to drop the at least the first request based on the confidence level, prefetch utilization, and memory resource utilization.

公开(公告)号：US09524166B2

公开(公告)日：2016-12-20

申请号：US13948800

申请日：2013-07-23

Applicant: International Business Machines Corporation

Inventor： Richard J. Eickemeyer ,  Tejas Karkhanis ,  Brian R. Konigsburg ,  David S. Levitan ,  Douglas R. G. Logan ,  Jose E. Moreira ,  Mauricio J. Serrano

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38 ,  G06F11/34

CPC classification number: G06F9/30058 ,  G06F9/3844 ,  G06F9/3848 ,  G06F9/3863 ,  G06F11/3466

Abstract: Tracking global history vector in high performance out of order superscalar processors, in one aspect, may comprise providing a shift register storing global history vector that stores branch predictions and outcomes. A counter is maintained to determine a number of bits to shift the shift register to recover branch history. In another aspect, the global history vector may be implemented with a circular buffer structure. Youngest and oldest pointers to the circular buffer are maintained and used in recovery.

Abstract translation: 跟踪全局历史向量在高性能无序超标量处理器中，一方面可以包括提供存储分支预测和结果的全局历史向量的移位寄存器。 维持计数器以确定移位寄存器以恢复分支历史的位数。 在另一方面，全局历史向量可以用循环缓冲结构来实现。 在循环缓冲区中保留最旧和最老的指针，并用于恢复。

公开(公告)号：US20230214218A1

公开(公告)日：2023-07-06

申请号：US17569951

申请日：2022-01-06

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Brian D. Barrick ,  Dung Q. Nguyen ,  Richard J. Eickemeyer ,  John B. Griswell, JR. ,  Balaram Sinharoy ,  Brian W. Thompto ,  Tu-An T. Nguyen

IPC: G06F9/30 ,  G06F9/38 ,  G06N5/04

CPC classification number: G06F9/30058 ,  G06F9/30043 ,  G06F9/30021 ,  G06F9/3855 ,  G06F9/3842 ,  G06N5/04

Abstract: A system, processor, programming product and/or method including: an instruction dispatch unit configured to dispatch instructions of a compare immediate-conditional branch instruction sequence; and a compare register having at least one entry to hold information in a plurality of fields. Operations include: writing information from a first instruction of the compare immediate-conditional branch instruction sequence into one or more of the plurality of fields in an entry in the compare register; writing an immediate field and the ITAG of a compare immediate instruction into the entry in the compare register; writing, in response to dispatching a conditional branch instruction, an inferred compare result value into the entry in the compare register; comparing a computed compare result value to the inferred compare result value stored in the entry in the compare register; and not execute the compare immediate instruction or the conditional branch instruction.

公开(公告)号：US20230063079A1

公开(公告)日：2023-03-02

申请号：US17410223

申请日：2021-08-24

Applicant: International Business Machines Corporation

Inventor： Mehul Patel ,  Nicholas R. Orzol ,  Dung Q. Nguyen ,  Balaram Sinharoy ,  Richard J. Eickemeyer ,  John B. Griswell, Jr. ,  Brian W. Thompto

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer processor includes an instruction pipeline configured to dispatch a plurality of branch-to-count (BCNT) instructions and an instruction fetch unit (IFU). The IFU is configured to execute an instruction loop for fetching a targeted number of BCNT instructions from the instruction pipeline and to monitor a loop counter that counts a number of fetched BCNT instructions that are actually fetched from the instruction pipeline in response to executing the instruction loop. The IFU resolves a final BCNT instruction included in the instruction loop in response to the number of fetched BCNT instructions reaching a target loop count value.

公开(公告)号：US11520591B2

公开(公告)日：2022-12-06

申请号：US16832845

申请日：2020-03-27

Applicant: International Business Machines Corporation

Inventor： Ehsan Fatehi ,  Richard J. Eickemeyer ,  John B. Griswell, Jr.

IPC: G06F9/38

Abstract: Processing data in an information handling system is disclosed that includes: in response to an event that triggers a flushing operation, calculate a finish ratio, wherein the finish ratio is a number of finished operations to a number of at least one of the group consisting of in-flight instructions, instructions pending in a processor pipeline, instructions issued to an issue queue, and instructions being processed in a processor execution unit; compare the calculated finish ratio to a threshold; and if the finish ratio is greater than the threshold, then do not perform the flushing operation. Also disclosed is moving the flush point.

公开(公告)号：US10078514B2

公开(公告)日：2018-09-18

申请号：US15151609

申请日：2016-05-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Richard J. Eickemeyer ,  Sheldon B. Levenstein ,  David S. Levitan ,  Mauricio J. Serrano ,  Brian W. Thompto

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/0862 ,  H04L12/743 ,  G06F12/0875

Abstract: A technique for operating a processor includes allocating an entry in a prefetch filter queue (PFQ) for a cache line address (CLA) in response to the CLA missing in an upper level instruction cache. In response to the CLA subsequently hitting in the upper level instruction cache, an associated prefetch value for the entry in the PFQ is updated. In response to the entry being aged-out of the PFQ, an entry in a backing array for the CLA and the associated prefetch value is allocated. In response to subsequently determining that prefetching is required for the CLA, the backing array is accessed to determine the associated prefetch value for the CLA. A cache line at the CLA and a number of sequential cache lines specified by the associated prefetch value in the backing array are then prefetched into the upper level instruction cache.