公开(公告)号：US11886342B2

公开(公告)日：2024-01-30

申请号：US17457135

申请日：2021-12-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aaron Dingler ,  Mohit Karve ,  Alper Buyuktosunoglu

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/0811 ,  G06F12/122 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/0891 ,  G06F12/122

Abstract: A method, system, and computer program product for augmenting cache replacement operations are provided. The method identifies a set of cache lines within a first cache level of a multilevel cache. A first candidate cache line is identified based on a first replacement scheme of the first cache level. A second candidate cache line is identified based on the first replacement scheme of the first cache level. A replacement cache line is selected for replacement in the first cache level. The replacement cache line is selected from the first candidate cache line and the second candidate cache line and based on the first replacement scheme of the first cache level and a second replacement scheme of a second cache level. The method removes the replacement cache line from the first cache level.

公开(公告)号：US11586440B2

公开(公告)日：2023-02-21

申请号：US17336240

申请日：2021-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Naga P. Gorti ,  Mohit Karve

IPC: G06F8/20 ,  G06F9/38

Abstract: A computer-implemented method of performing a link stack based prefetch augmentation using a sequential prefetching includes observing a call instruction in a program being executed, and pushing a return address onto a link stack for processing the next instruction. A stream of instructions is prefetched starting from a cached line address of the next instruction and is stored in an instruction cache.

公开(公告)号：US11561796B2

公开(公告)日：2023-01-24

申请号：US16929208

申请日：2020-07-15

Applicant: International Business Machines Corporation

Inventor： Naga P. Gorti ,  Mohit Karve

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/0875

Abstract: A computer-implemented method to prefetch non-sequential instruction addresses (I/A) includes, determining, by a prefetch system, a first access attempt of a first I/A in a cache is a first miss, wherein the first I/A is included in a string of I/A's. The method further includes storing the first I/A in a linked miss-to-miss (LMTM) table. The method also includes determining a second access attempt of a second I/A in the cache is a second miss, wherein the second I/A is included in the string of I/A's. The method includes linking, in the LMTM table, the second miss to the first miss. The method also includes prefetching, in response to a third access attempt of the first I/A, the second I/A in the cache.

公开(公告)号：US11481219B2

公开(公告)日：2022-10-25

申请号：US16868793

申请日：2020-05-07

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Edmund Joseph Gieske ,  George W. Rohrbaugh, III

IPC: G06F9/38 ,  G06F12/0875 ,  G06F9/30

Abstract: An information handling system, method, and processor that detects a store instruction for data in a processor where the store instruction is a reliable indicator of a future load for the data; in response to detecting the store instruction, sends a prefetch request to memory for an entire cache line containing the data referenced in the store instruction, and preferably only the single cache line containing the data; and receives, in response to the prefetch request, the entire cache line containing the data referenced in the store instruction.

公开(公告)号：US20210034528A1

公开(公告)日：2021-02-04

申请号：US16528901

申请日：2019-08-01

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  VIVEK BRITTO ,  George W. Rohrbaugh, III

IPC: G06F12/0862

Abstract: Disclosed is a computer implemented method and system to dynamically adjust prefetch depth, the method comprising, identifying a first prefetch stream, wherein the first prefetch stream is identified in a prefetch request queue (PRQ), and wherein the first prefetch stream includes a first prefetch depth. The method also comprises determining a number of inflight prefetches, and comparing, a number of prefetch machines against the number of inflight prefetches, wherein each of the prefetch machines is configured to monitor one prefetch request. The method further includes adjusting, in response to the comparing, the first prefetch depth of the first prefetch stream.

公开(公告)号：US20200081714A1

公开(公告)日：2020-03-12

申请号：US16125974

申请日：2018-09-10

Applicant: International Business Machines Corporation

Inventor： Vivek Britto ,  Mohit Karve ,  George W. Rohrbaugh, III ,  Brian W. Thompto

IPC: G06F9/38 ,  G06F12/0875

Abstract: A computer system, processor, and method for processing information is disclosed that includes allocating a prefetch stream; providing a protection bubble to a plurality of cachelines for the allocated prefetch stream; accessing a cacheline; and preventing allocation of a different prefetch stream if the accessed cacheline is within the protection bubble. The system, processor and method in an aspect further includes providing a safety zone to a plurality of cachelines for the allocated prefetch stream, and advancing the prefetch stream if the accessed cacheline is one of the plurality of cachelines in the safety zone. In an embodiment, the number of cachelines within the safety zone is less than the number of cachelines in the protection bubble.

公开(公告)号：US11989136B2

公开(公告)日：2024-05-21

申请号：US17483136

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Brian W. Thompto

IPC: G06F12/1036 ,  G06F12/0882 ,  G06F12/1009 ,  G06F13/16

CPC classification number: G06F12/1036 ,  G06F12/0882 ,  G06F12/1009 ,  G06F13/1668 ,  G06F2212/7201

Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.

公开(公告)号：US11816034B2

公开(公告)日：2023-11-14

申请号：US17079619

申请日：2020-10-26

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Naga P. Gorti

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: A Bloom filter is used to track contents of a cache. A system checks the Bloom filter before deciding whether to prefetch an address (by hashing the address and checking a value of the Bloom filter at an index based on the hash). This allows the system to utilize more aggressive prefetching schemes by reducing the risk of wasteful redundant prefetch operations.

公开(公告)号：US11520588B2

公开(公告)日：2022-12-06

申请号：US16435651

申请日：2019-06-10

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Edmund Joseph Gieske

IPC: G06F9/38 ,  G06F12/0862

Abstract: Disclosed is a computer-implemented method to increase the efficiency of a prefetch system. The method includes receiving a system call including an instruction address. The method includes determining a confidence score. The method further includes creating an entry, including the instruction address, an associated data address, and the confidence score. The method includes determining the instruction address is not present in a history table, where the history table includes a plurality of entries. The method further includes determining, in response to adding the first entry to the history table, a second entry is evicted from the history table. The method includes entering the second entry into a filter table in response to determining the second confidence score is a moderate confidence score, where the moderate confidence score is any confidence score that is greater than a predefined low threshold and less than a predefined high threshold.

公开(公告)号：US11301386B2

公开(公告)日：2022-04-12

申请号：US16528901

申请日：2019-08-01

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Vivek Britto ,  George W. Rohrbaugh, III

IPC: G06F12/0862

Abstract: Disclosed is a computer implemented method and system to dynamically adjust prefetch depth, the method comprising, identifying a first prefetch stream, wherein the first prefetch stream is identified in a prefetch request queue (PRQ), and wherein the first prefetch stream includes a first prefetch depth. The method also comprises determining a number of inflight prefetches, and comparing, a number of prefetch machines against the number of inflight prefetches, wherein each of the prefetch machines is configured to monitor one prefetch request. The method further includes adjusting, in response to the comparing, the first prefetch depth of the first prefetch stream.