公开(公告)号：US20200210346A1

公开(公告)日：2020-07-02

申请号：US16237780

申请日：2019-01-02

Applicant: International Business Machines Corporation

Inventor： VIVEK BRITTO ,  BRYANT COCKCROFT ,  John Schumann ,  Tharunachalam Pindicura ,  SHRICHARAN SRIVATSAN ,  YAN XIA ,  AISHWARYA DHANDAPANI

IPC: G06F12/1027 ,  G06F12/0862

Abstract: Examples of techniques for software translation prefetch instructions are described herein. An aspect includes, based on encountering a translation prefetch instruction in software that is being executed by a processor, determining whether an address translation corresponding to the translation prefetch instruction is located in a translation lookaside buffer (TLB) of the processor. Another aspect includes, based on determining that the address translation is not located in the TLB, issuing an address translation request corresponding to the translation prefetch instruction. Another aspect includes storing an address translation corresponding to the address translation request in the TLB.

公开(公告)号：US20220309001A1

公开(公告)日：2022-09-29

申请号：US17215296

申请日：2021-03-29

Applicant: International Business Machines Corporation

Inventor： David Campbell ,  Bryan Lloyd ,  George W. Rohrbaugh, III ,  VIVEK BRITTO ,  Mohit Karve

IPC: G06F12/0862

Abstract: A computer system includes a processor and a prefetch engine. The processor is configured to generate a demand access stream. The prefetch engine is configured to generate a first prefetch request and a second prefetch request based on the demand access stream, to output the first prefetch request to a first translation lookaside buffer (TLB), and to output the second prefetch request to a second TLB that is different from the first TLB. The processor performs a first TLB lookup in the first TLB based on one of the demand access stream or the first prefetch request, and performs a second TLB lookup in the second TLB based on the second prefetch request.

公开(公告)号：US20220012393A1

公开(公告)日：2022-01-13

申请号：US16922514

申请日：2020-07-07

Applicant: International Business Machines Corporation

Inventor： Tharunachalam Pindicura ,  YAN XIA ,  KAREN YOKUM ,  VIVEK BRITTO ,  SHRICHARAN ,  AISHWARYA DHANDAPANI

IPC: G06F30/331 ,  G06F30/333 ,  G06F11/36 ,  G06F11/14 ,  G06F9/38

Abstract: Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.

公开(公告)号：US20210034529A1

公开(公告)日：2021-02-04

申请号：US16528917

申请日：2019-08-01

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Edmund Joseph Gieske ,  VIVEK BRITTO ,  George W. Rohrbaugh, III

IPC: G06F12/0862

Abstract: Disclosed is a computer implemented method to dynamically adjust prefetch depth, the method comprising sending, to a first prefetch machine, a first prefetch request configured to fetch a first data address from a first stream at a first depth to a lower level cache. The method also comprises sending, to a second prefetcher, a second prefetch request configured to fetch the first data address from the first stream at a second depth to a highest-level cache. The method further comprises determining the first data address is not in the lower level cache, determining, that the first prefetch request is in the first prefetch machine, and determining, in response to the first prefetch request being in the first prefetch machine, that the first stream is at steady state. The method comprises adjusting, in response to determining that the first stream is at steady state, the first depth.

公开(公告)号：US20220004680A1

公开(公告)日：2022-01-06

申请号：US16918675

申请日：2020-07-01

Applicant: International Business Machines Corporation

Inventor： John A. Schumann ,  Tharunachalam Pindicura ,  SHRICHARAN SRIVATSAN ,  VIVEK BRITTO ,  Madhumitha Venkataraman

IPC: G06F30/20 ,  G06F9/445 ,  G06F9/455

Abstract: A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.

公开(公告)号：US20210365294A1

公开(公告)日：2021-11-25

申请号：US16881628

申请日：2020-05-22

Applicant: International Business Machines Corporation

Inventor： Tharunachalam Pindicura ,  SHRICHARAN SRIVATSAN ,  VIVEK BRITTO ,  YAN XIA ,  AISHWARYA DHANDAPANI

IPC: G06F9/50 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36

Abstract: A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.

公开(公告)号：US20210034528A1

公开(公告)日：2021-02-04

申请号：US16528901

申请日：2019-08-01

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  VIVEK BRITTO ,  George W. Rohrbaugh, III

IPC: G06F12/0862

Abstract: Disclosed is a computer implemented method and system to dynamically adjust prefetch depth, the method comprising, identifying a first prefetch stream, wherein the first prefetch stream is identified in a prefetch request queue (PRQ), and wherein the first prefetch stream includes a first prefetch depth. The method also comprises determining a number of inflight prefetches, and comparing, a number of prefetch machines against the number of inflight prefetches, wherein each of the prefetch machines is configured to monitor one prefetch request. The method further includes adjusting, in response to the comparing, the first prefetch depth of the first prefetch stream.