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公开(公告)号：US10445100B2
公开(公告)日：2019-10-15
申请号：US15177394
申请日：2016-06-09
发明人： Salma Ayub , Joshua W. Bowman , Jeffrey C. Brownscheidle , Sundeep Chadha , Dhivya Jeganathan , Dung Q. Nguyen , Salim A. Shah , Brian W. Thompto
IPC分类号： G06F9/38
摘要： Methods and apparatus for transmitting data between execution slices of a multi-slice processor including receiving, by an execution slice, a broadcast message comprising an instruction tag (ITAG) for a producer instruction, a latency, and a source identifier; determining that an issue queue in the execution slice comprises an ITAG for a consumer instruction, wherein the consumer instruction depends on result data from the producer instruction; calculating a cycle countdown using the latency and the source identifier; determining that the cycle countdown has expired; and in response to determining that the cycle countdown has expired, reading the result data from the producer instruction.
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公开(公告)号：US20170322812A1
公开(公告)日：2017-11-09
申请号：US15661422
申请日：2017-07-27
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836
摘要： In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions is represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A 1-hot signal is generated that identifies an oldest ready instruction in the first age array and a 1-hot signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
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3.发明申请TECHNIQUES FOR IMPROVING ISSUE OF INSTRUCTIONS WITH VARIABLE LATENCIES IN A MICROPROCESSOR 审中-公开用于改进在微处理器中使用可变延迟的指令的技术公开(公告)号：US20160371090A1
公开(公告)日：2016-12-22
申请号：US15070672
申请日：2016-03-15
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3855
摘要： Techniques are disclosed for issuing instructions in a processor. According to one embodiment of the present disclosure, an instruction tag is broadcast to wake up a plurality of instructions stored in an issue queue that are dependent on an issued instruction associated with the instruction tag. Each of the plurality of instructions has an execution latency. One or more of the instructions having an execution that will collide with an execution of one of the issued instructions if issued in a next clock cycle are identified based on the execution latencies. The identified one or more instructions are delayed from issue by at least one clock cycle after the next clock cycle.
摘要翻译： 公开了用于在处理器中发出指令的技术。 根据本公开的一个实施例，广播指令标签以唤醒存储在发布队列中的多个指令，这些指令取决于与指令标签相关联的发出的指令。 多个指令中的每一个具有执行等待时间。 基于执行延迟来识别具有执行的一个或多个指令，该执行将与下一个时钟周期中发出的指令之一的执行相冲突。 所识别的一个或多个指令在下一个时钟周期之后至少一个时钟周期被延迟。
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公开(公告)号：US11150909B2
公开(公告)日：2021-10-19
申请号：US14965957
申请日：2015-12-11
摘要： In an approach for decreasing a rate of logic voltage level transitions in a multiplexor, one of a plurality of inputs to a multiplexor is selected with a first multiplexor select value at a first clock, wherein each input to the multiplexor is identified as one of i) valid and ii) invalid and the first multiplexor select value is latched in a latch until the first multiplexor select value is replaced by a second multiplexor select value. The second multiplexor select value is determined. The second multiplexor select value is applied to the multiplexor at a second clock if and only if the second multiplexor select value is different from the first multiplexor select value and the second multiplexor select value selects a valid input, wherein the second clock follows the first clock. Subsequent to applying the second multiplexor select value, the second multiplexor value is latched in the latch.
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公开(公告)号：US20180217843A1
公开(公告)日：2018-08-02
申请号：US15939367
申请日：2018-03-29
发明人： Salma Ayub , Jeffrey C. Brownscheidle , Sundeep Chadha , Dung Q. Nguyen , Tu-An T. Nguyen , Salim A. Shah , Brian W. Thompto
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3855 , G06F9/3867 , G06F9/3887
摘要： Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.
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公开(公告)号：US20170269938A1
公开(公告)日：2017-09-21
申请号：US15617287
申请日：2017-06-08
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836
摘要： In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A 1-hot signal is generated that identifies an oldest ready instruction in the first age array and a 1-hot signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
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公开(公告)号：US20170031686A1
公开(公告)日：2017-02-02
申请号：US15145835
申请日：2016-05-04
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836
摘要： In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
摘要翻译： 在用于在发布队列中选择和发出最早的就绪指令的方法中，一个或多个处理器在发布队列中接收一个或多个指令。 已准备好执行指令。 说明的年龄用第一个年龄组表示。 为每个子集中的指令的年龄段的子集年龄数组生成指令的一个或多个子集。 生成主要信号，其识别第一年龄数组中的最早的就绪指令，并且同时生成识别每个子集龄数组中最早的就绪指令的子集信号。 在子集信号的子集年龄阵列中表示的每个子集信号选择候选指令，其中候选指令是子集年龄阵列中的最早就绪指令。 选择主要信号并发出候选指令。
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公开(公告)号：US09367322B1
公开(公告)日：2016-06-14
申请号：US14809291
申请日：2015-07-27
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836
摘要： In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
摘要翻译： 在用于在发布队列中选择和发出最早的就绪指令的方法中，一个或多个处理器在发布队列中接收一个或多个指令。 已准备好执行指令。 说明的年龄用第一个年龄组表示。 为每个子集中的指令的年龄段的子集年龄数组生成指令的一个或多个子集。 生成主要信号，其识别第一年龄数组中的最早的就绪指令，并且同时生成识别每个子集龄数组中最早的就绪指令的子集信号。 在子集信号的子集年龄阵列中表示的每个子集信号选择候选指令，其中候选指令是子集年龄阵列中的最早就绪指令。 选择主要信号并发出候选指令。
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公开(公告)号：US10942745B2
公开(公告)日：2021-03-09
申请号：US16141285
申请日：2018-09-25
发明人： Salma Ayub , Jeffrey C. Brownscheidle , Sundeep Chadha , Dung Q. Nguyen , Tu-An T. Nguyen , Salim A. Shah , Brian W. Thompto
IPC分类号： G06F9/38
摘要： Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.
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10.发明授权公开(公告)号：US10318294B2
公开(公告)日：2019-06-11
申请号：US15186744
申请日：2016-06-20
发明人： Khandker N. Adeeb , Joshua W. Bowman , Jeffrey C. Brownscheidle , Brandon R. Goddard , Dung Q. Nguyen , Tu-An T. Nguyen , Brian D. Victor , Brendan M. Wong
IPC分类号： G06F9/30
摘要： Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.
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