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公开(公告)号：US10031757B2
公开(公告)日：2018-07-24
申请号：US15042902
申请日：2016-02-12
发明人： Jeffrey C. Brownscheidle , Sundeep Chadha , Maureen A. Delaney , Dhivya Jeganathan , Dung Q. Nguyen , Salim A. Shah
IPC分类号： G06F9/38
摘要： Operation of a multi-slice processor that includes execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Such a multi-slice processor includes a plurality of execution slices and a dispatch network of the multi-slice processor implementing a hardware level mechanism to overcome a system hang. Operation of such a multi-slice processor includes, storing, in one or more logical units of a plurality of logical units of an age array, a logical value representing a relative age between instructions; propagating, in response to a current instruction being in a hang state, a hang signal to the plurality of logical units of the age array; in response to the hang signal, generating, from the plurality of logical units, a plurality of logical output values indicating a next instruction ready for execution; and issuing the next instruction for execution.
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2.发明授权公开(公告)号：US09983879B2
公开(公告)日：2018-05-29
申请号：US15059853
申请日：2016-03-03
发明人： Jeffrey C. Brownscheidle , Sundeep Chadha , Maureen A. Delaney , Dhivya Jeganathan , Dung Q. Nguyen , Salim A. Shah
CPC分类号： G06F9/3836 , G06F9/30189 , G06F9/3838 , G06F9/3851 , G06F9/3855 , G06F9/3861 , G06F9/3865 , G06F9/3867 , G06F9/3885 , G06F9/3891
摘要： Operation of a multi-slice processor that includes execution slices implementing dynamic switching of instruction issuance order. Such a multi-slice processor includes determining a current issuance order for a plurality of instructions and a change in an operating condition of the multi-slice processor; responsive to determining the change in the operating condition, determining an alternate issuance order for the plurality of instructions; and responsive to determining the alternate issuance order, switching from the current issuance order for the plurality of instructions to the alternate issuance order for the plurality of instructions.
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公开(公告)号：US20170168830A1
公开(公告)日：2017-06-15
申请号：US14965957
申请日：2015-12-11
CPC分类号： G06F9/3836 , G06F9/30 , G06F9/30007 , G06F9/30072
摘要： In an approach for decreasing a rate of logic voltage level transitions in a multiplexor, one of a plurality of inputs to a multiplexor is selected with a first multiplexor select value at a first clock, wherein each input to the multiplexor is identified as one of i) valid and ii) invalid and the first multiplexor select value is latched in a latch until the first multiplexor select value is replaced by a second multiplexor select value. The second multiplexor select value is determined. The second multiplexor select value is applied to the multiplexor at a second clock if and only if the second multiplexor select value is different from the first multiplexor select value and the second multiplexor select value selects a valid input, wherein the second clock follows the first clock. Subsequent to applying the second multiplexor select value, the second multiplexor value is latched in the latch.
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公开(公告)号：US20180232230A1
公开(公告)日：2018-08-16
申请号：US15898969
申请日：2018-02-19
发明人： Brian D. Barrick , Sundeep Chadha , Maureen A. Delaney , Thao T. Doan , Michael J. Genden , Rokesh Jayasundar , Dung Q. Nguyen , David R. Terry
IPC分类号： G06F9/30 , G06F9/38 , G06F12/0831 , G06F12/0875 , G06F13/42
CPC分类号： G06F9/3851 , G06F9/3001 , G06F9/30043 , G06F9/3828 , G06F9/3836 , G06F9/384 , G06F9/3891 , G06F13/4068 , G06F13/4282
摘要： Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
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公开(公告)号：US09971600B2
公开(公告)日：2018-05-15
申请号：US14751730
申请日：2015-06-26
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/3814 , G06F9/3836 , G06F9/3855
摘要： Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.
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公开(公告)号：US09389870B1
公开(公告)日：2016-07-12
申请号：US14977962
申请日：2015-12-22
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836
摘要： In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A 1-hot signal is generated that identifies an oldest ready instruction in the first age array and a 1-hot signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
摘要翻译： 在用于在发布队列中选择和发出最早的就绪指令的方法中，一个或多个处理器在发布队列中接收一个或多个指令。 已准备好执行指令。 说明的年龄用第一个年龄组表示。 为每个子集中的指令的年龄段的子集年龄数组生成指令的一个或多个子集。 生成1-hot信号，其识别第一年龄数组中最早的就绪指令，并且同时生成识别每个子集龄数组中最早的就绪指令的1-hot信号。 在子集信号的子集年龄阵列中表示的每个子集信号选择候选指令，其中候选指令是子集年龄阵列中的最早就绪指令。 选择主要信号并发出候选指令。
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公开(公告)号：US11150909B2
公开(公告)日：2021-10-19
申请号：US14965957
申请日：2015-12-11
摘要： In an approach for decreasing a rate of logic voltage level transitions in a multiplexor, one of a plurality of inputs to a multiplexor is selected with a first multiplexor select value at a first clock, wherein each input to the multiplexor is identified as one of i) valid and ii) invalid and the first multiplexor select value is latched in a latch until the first multiplexor select value is replaced by a second multiplexor select value. The second multiplexor select value is determined. The second multiplexor select value is applied to the multiplexor at a second clock if and only if the second multiplexor select value is different from the first multiplexor select value and the second multiplexor select value selects a valid input, wherein the second clock follows the first clock. Subsequent to applying the second multiplexor select value, the second multiplexor value is latched in the latch.
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公开(公告)号：US20170269938A1
公开(公告)日：2017-09-21
申请号：US15617287
申请日：2017-06-08
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836
摘要： In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A 1-hot signal is generated that identifies an oldest ready instruction in the first age array and a 1-hot signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
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公开(公告)号：US20170031686A1
公开(公告)日：2017-02-02
申请号：US15145835
申请日：2016-05-04
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836
摘要： In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
摘要翻译： 在用于在发布队列中选择和发出最早的就绪指令的方法中，一个或多个处理器在发布队列中接收一个或多个指令。 已准备好执行指令。 说明的年龄用第一个年龄组表示。 为每个子集中的指令的年龄段的子集年龄数组生成指令的一个或多个子集。 生成主要信号，其识别第一年龄数组中的最早的就绪指令，并且同时生成识别每个子集龄数组中最早的就绪指令的子集信号。 在子集信号的子集年龄阵列中表示的每个子集信号选择候选指令，其中候选指令是子集年龄阵列中的最早就绪指令。 选择主要信号并发出候选指令。
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公开(公告)号：US09367322B1
公开(公告)日：2016-06-14
申请号：US14809291
申请日：2015-07-27
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F9/3836
摘要： In an approach for selecting and issuing an oldest ready instruction in an issue queue, one or more processors receive one or more instructions in an issue queue. Ready to execute instructions are identified. An age of the instructions are represented in a first age array. One or more subsets of the instructions are generated for subset age arrays that each hold an age of the instructions in a subset. A major signal is generated that identifies an oldest ready instruction in the first age array and a subset signal is simultaneously generated that identifies an oldest ready instruction in each subset age array. A candidate instruction is selected with each subset signal that is represented in the subset age array of the subset signal, wherein a candidate instruction is an oldest ready instruction in the subset age array. A candidate instruction is selected with the major signal and issued.
摘要翻译： 在用于在发布队列中选择和发出最早的就绪指令的方法中，一个或多个处理器在发布队列中接收一个或多个指令。 已准备好执行指令。 说明的年龄用第一个年龄组表示。 为每个子集中的指令的年龄段的子集年龄数组生成指令的一个或多个子集。 生成主要信号，其识别第一年龄数组中的最早的就绪指令，并且同时生成识别每个子集龄数组中最早的就绪指令的子集信号。 在子集信号的子集年龄阵列中表示的每个子集信号选择候选指令，其中候选指令是子集年龄阵列中的最早就绪指令。 选择主要信号并发出候选指令。
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