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1.发明申请公开(公告)号：US20200159882A1
公开(公告)日：2020-05-21
申请号：US16194381
申请日：2018-11-18
IPC分类号： G06F17/50
摘要： A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.
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公开(公告)号：US10140127B2
公开(公告)日：2018-11-27
申请号：US15898969
申请日：2018-02-19
发明人： Brian D. Barrick , Sundeep Chadha , Maureen A. Delaney , Thao T. Doan , Michael J. Genden , Rokesh Jayasundar , Dung Q. Nguyen , David R. Terry
摘要： Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
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3.发明授权公开(公告)号：US10803224B2
公开(公告)日：2020-10-13
申请号：US16194381
申请日：2018-11-18
IPC分类号： G06F30/392 , G06F111/04 , G06F119/06 , G06F119/12
摘要： A design system accesses at least one placement template for at least one structured soft block composed of a pre-defined set of cells with relative placement information for the pre-defined set of cells. The design system optimizes implementation of the at least one structured soft block by propagating constants while preserving relative placement structure of the pre-defined set of cells within each at least one structured soft block according to the respective at least one placement template accessed for the at least one structured soft block.
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公开(公告)号：US20180232230A1
公开(公告)日：2018-08-16
申请号：US15898969
申请日：2018-02-19
发明人： Brian D. Barrick , Sundeep Chadha , Maureen A. Delaney , Thao T. Doan , Michael J. Genden , Rokesh Jayasundar , Dung Q. Nguyen , David R. Terry
IPC分类号： G06F9/30 , G06F9/38 , G06F12/0831 , G06F12/0875 , G06F13/42
CPC分类号： G06F9/3851 , G06F9/3001 , G06F9/30043 , G06F9/3828 , G06F9/3836 , G06F9/384 , G06F9/3891 , G06F13/4068 , G06F13/4282
摘要： Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
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公开(公告)号：US10127047B2
公开(公告)日：2018-11-13
申请号：US15898657
申请日：2018-02-18
发明人： Brian D. Barrick , Sundeep Chadha , Maureen A. Delaney , Thao T. Doan , Michael J. Genden , Rokesh Jayasundar , Dung Q. Nguyen , David R. Terry
摘要： Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
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公开(公告)号：US09952874B2
公开(公告)日：2018-04-24
申请号：US15046569
申请日：2016-02-18
发明人： Brian D. Barrick , Sundeep Chadha , Maureen A. Delaney , Thao T. Doan , Michael J. Genden , Rokesh Jayasundar , Dung Q. Nguyen , David R. Terry
CPC分类号： G06F9/3851 , G06F9/3001 , G06F9/30043 , G06F9/3844 , G06F13/4068 , G06F13/4282
摘要： Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
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公开(公告)号：US09952861B2
公开(公告)日：2018-04-24
申请号：US14969588
申请日：2015-12-15
发明人： Brian D. Barrick , Sundeep Chadha , Maureen A. Delaney , Thao T. Doan , Michael J. Genden , Rokesh Jayasundar , Dung Q. Nguyen , David R. Terry
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08 , G06F13/42 , G06F12/0875 , G06F12/0831
CPC分类号： G06F9/3851 , G06F9/3001 , G06F9/30043 , G06F9/3844 , G06F13/4068 , G06F13/4282
摘要： Operation of a multi-slice processor including execution slices and load/store slices, where the load/store slices are coupled to the execution slices via a results bus and the results bus includes segments assigned to carry results of a different instruction type, includes: receiving a producer instruction that includes an identifier of an instruction type and an identifier of the producer instruction, including storing the identifier of the instruction type and the identifier of the producer instruction in an entry of a register; receiving a source instruction dependent upon the result of the producer instruction including storing, in an issue queue, the source instruction, the identifier of the instruction type of the producer instruction, and an identifier of the producer instruction; and snooping the identifier of the producer instruction only from the segment of the results bus assigned to carry results of the instruction type of the producer instruction.
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