公开(公告)号：US11068267B2

公开(公告)日：2021-07-20

申请号：US16392722

申请日：2019-04-24

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Brandon Goddard ,  Dung Q. Nguyen ,  Joshua W. Bowman ,  Brian D. Barrick ,  Susan Eisen ,  Salma Ayub ,  Christopher M. Mueller

IPC: G06F9/30 ,  G06F9/48 ,  G06F11/14

Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.

公开(公告)号：US10977034B2

公开(公告)日：2021-04-13

申请号：US16182760

申请日：2018-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kenneth L. Ward ,  Susan E. Eisen ,  Glenn O. Kincaid ,  Dung Q. Nguyen ,  Deepak K. Singh ,  Gaurav Mittal ,  Christopher M. Mueller

IPC: G06F9/30 ,  G06F9/38

Abstract: A computer-implemented method, computer program product, and computer processing system are provided. The method includes processing, by a superscalar processing pipeline, respective sets of instructions in respective instruction processing cycles using an Instruction Completion Table (ICT) with a Ready-To-Complete (RTC) vector. The ICT includes a plurality of entries, each corresponding to a respective one of the instructions. A Next-To-Complete (NTC) instruction from among the respective sets of instructions is computed using the RTC vector.

公开(公告)号：US20170293488A1

公开(公告)日：2017-10-12

申请号：US15093172

申请日：2016-04-07

Applicant: International Business Machines Corporation

Inventor： Kurt A. Feiste ,  Christopher M. Mueller ,  Dung Q. Nguyen ,  Eula F. Tolentino ,  Tien T. Tran ,  Jing Zhang

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3009 ,  G06F9/3012 ,  G06F9/30189 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/46 ,  G06F9/461

Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.

公开(公告)号：US11360779B2

公开(公告)日：2022-06-14

申请号：US17109583

申请日：2020-12-02

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Salma Ayub ,  Brian D. Barrick ,  Joshua W. Bowman ,  Susan E. Eisen ,  Brandon Goddard ,  Christopher M. Mueller ,  Dung Q. Nguyen

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.

公开(公告)号：US10423423B2

公开(公告)日：2019-09-24

申请号：US14869379

申请日：2015-09-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Susan E. Eisen ,  David A. Hrusecky ,  Christopher M. Mueller ,  Dung Q. Nguyen ,  A. James Van Norstrand, Jr. ,  Kenneth L. Ward

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0897

Abstract: Within a processor, speculative finishes of load instructions only are tracked in a speculative finish table by maintaining an oldest load instruction of a thread in the speculative finish table after data is loaded for the oldest load instruction, wherein a particular queue index tag assigned to the oldest load instruction by an execution unit points to a particular entry in the speculative finish table, wherein the oldest load instruction is waiting to be finished dependent upon an error check code result. Responsive to a flow unit receiving the particular queue index tag with an indicator that the error check code result for data retrieved for the oldest load instruction is good, finishing the oldest load instruction in the particular entry pointed to by the queue index tag and writing an instruction tag stored in the entry for the oldest load instruction out of the speculative finish table for completion.

公开(公告)号：US10248426B2

公开(公告)日：2019-04-02

申请号：US15163314

申请日：2016-05-24

Applicant: International Business Machines Corporation

Inventor： Brian D. Barrick ,  Steven J. Battle ,  Joshua W. Bowman ,  Christopher M. Mueller ,  Dung Q. Nguyen ,  David R. Terry ,  Eula Faye Tolentino ,  Jing Zhang

IPC: G06F9/38

Abstract: Techniques are disclosed for restoring register data in a processor. In one embodiment, a method includes receiving an instruction to flush one or more general purpose registers (GPRs) in a processor. The method also includes determining history buffer entries of a history buffer to be restored to the one or more GPRs. The method includes creating a mask vector that indicates which history buffer entries will be restored to the one or more GPRs. The method further includes restoring the indicated history buffer entries to the one or more GPRs. As each indicated history buffer entry is restored, the method includes updating the mask vector to indicate which history buffer entries have been restored.

公开(公告)号：US11269647B2

公开(公告)日：2022-03-08

申请号：US15845871

申请日：2017-12-18

Applicant: International Business Machines Corporation

Inventor： Kenneth L. Ward ,  Susan E. Eisen ,  Dung Q. Nguyen ,  Glenn O. Kincaid ,  Christopher M. Mueller ,  Tu-An T. Nguyen ,  Gaurav Mittal ,  Deepak K. Singh

IPC: G06F9/30 ,  G06F9/38

Abstract: A simultaneous multithreading processor and related method of operating are disclosed. The method comprises dispatching portions of a first instruction to be executed by a respective plurality of execution units of the processor; receiving, at an instruction completion table of the processor, respective finish reports responsive to execution of the portions of the first instruction; determining, using the received finish reports, that all of the portions of the first instruction have been executed; and updating the instruction completion table to indicate that the first instruction is ready for completion.

公开(公告)号：US11086630B1

公开(公告)日：2021-08-10

申请号：US16802679

申请日：2020-02-27

Applicant: International Business Machines Corporation

Inventor： Kenneth L. Ward ,  Susan Eisen ,  Christopher M. Mueller ,  Glenn O. Kincaid ,  Dhivya Jeganathan

IPC: G06F9/30 ,  G06F9/38

Abstract: A computer system includes a dispatch stage configured to dispatch a plurality of instructions in a program order, and an issue stage configured to issue at least one instruction among the plurality of instructions. The computer system further includes an execution stage configured to execute the at least one instruction to generate a finish report and to determine the at least one instruction is one of an exception-free instruction or an exception instruction. In response to determining the exception-free instruction, a first finish report associated with the exception-free instruction is output to a completion stage. In response to determining the exception instruction, a second finish report associated with the exception instruction is output to an exception unit so as to halt output of the second finish report to the completion stage.

公开(公告)号：US20200341767A1

公开(公告)日：2020-10-29

申请号：US16392722

申请日：2019-04-24

Applicant: International Business Machines Corporation

Inventor： Steven J. Battle ,  Brandon Goddard ,  Dung Q. Nguyen ,  Joshua W. Bowman ,  Brian D. Barrick ,  Susan Eisen ,  Salma Ayub ,  Christopher M. Mueller

IPC: G06F9/30 ,  G06F11/14 ,  G06F9/48

Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.

公开(公告)号：US10102001B2

公开(公告)日：2018-10-16

申请号：US15938987

申请日：2018-03-28

Applicant: International Business Machines Corporation

Inventor： Kurt A. Feiste ,  Christopher M. Mueller ,  Dung Q. Nguyen ,  Eula A. Tolentino ,  Tien T. Tran ,  Jing Zhang

IPC: G06F9/30 ,  G06F9/46 ,  G06F9/38 ,  G06F9/34

Abstract: Supplemental instruction dispatch may be used in some instances in a parallel slice processor to dispatch additional instructions, referred to as supplemental instructions, to supplemental instruction ports of execution slices and using primary instruction ports of one or more execution slices to supply one or more source operands for such supplemental instructions. In addition, in some instances, in lieu of or in addition to supplemental instruction dispatch, selective slice partitioning may be used to selectively partition groups of execution slices in a parallel slice processor based upon a threading mode within which such execution slices are executing.