公开(公告)号：US20150035075A1

公开(公告)日：2015-02-05

申请号：US14515702

申请日：2014-10-16

Applicant: International Business Machines Corporation

Inventor： Mohit Bajaj ,  Kota V.R.M. Murali ,  Rahul Nayak ,  Edward J. Nowak ,  Rajan K. Pandey

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/7845

Abstract: A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.

Abstract translation: 栅极电介质层和功函数材料层的叠层淀积在多个半导体材料部分上，半导体材料部分可以是半导体衬底中的多个半导体鳍片或多个有源区域。 施加第一应力的第一栅极导体材料形成在位于第一半导体材料部分上的功函数材料层的第一部分上，并且施加第二应力的第二栅极导体材料形成在位于 在第二半导体材料部分上。 第一和第二应力在极性和大小中的至少一个方面是不同的，从而在功函数材料层的第一和第二部分中引起不同的应变。 不同的应变导致功函数材料层的第一和第二部分中的功函数不同地移动，从而提供具有多个不同工作功能的装置。

公开(公告)号：US20160133730A1

公开(公告)日：2016-05-12

申请号：US14876006

申请日：2015-10-06

Applicant: International Business Machines Corporation

Inventor： Mohit Bajaj ,  Suresh Gundapaneni ,  Aniruddha Konar ,  Kota V.R.M. Murali ,  Edward J. Nowak

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66977 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/78645 ,  H01L29/78648 ,  H01L49/003

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.

公开(公告)号：US20170256664A1

公开(公告)日：2017-09-07

申请号：US15598519

申请日：2017-05-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Aveek N. Chatterjee ,  Kota V.R.M. Murali ,  Ninad D. Sathaye ,  Rajesh Sathiyanarayanan

IPC: H01L31/054 ,  H02S40/42 ,  H02S20/10 ,  H01L31/048 ,  H02S20/30 ,  H02S20/20

CPC classification number: H01L31/0547 ,  F24S23/71 ,  F24S70/30 ,  F24S80/45 ,  H01L31/048 ,  H02S20/10 ,  H02S20/20 ,  H02S20/30 ,  H02S20/32 ,  H02S40/425 ,  Y02E10/40 ,  Y02E10/52 ,  Y02E10/544

Abstract: A method including installing solar pods at varying heights on a tower, where a size of each of the solar pods is inversely related its installation height on the tower, each of the solar pods including a transparent ovoid enclosure symmetrical about an axis, and a reflector and a solar cell both contained within the transparent ovoid enclosure, the solar cell positioned at a common focal point of the reflector such that substantially all light reflected by the reflector is directed at the solar cell.

公开(公告)号：US20160133303A1

公开(公告)日：2016-05-12

申请号：US14534205

申请日：2014-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  Kota V.R.M. Murali ,  Edward J. Nowak

IPC: G11C7/10 ,  H03K5/13 ,  G11C11/419 ,  H01L21/768

CPC classification number: G11C7/106 ,  G11C7/02 ,  H01L21/76895 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H03K5/13

Abstract: Some embodiments of the present invention may include one, or more, of the following features, characteristics or advantages: (i) latch device including multiple Ecrit material regions all electrically connected to a common terminal (sometimes structured and shaped in the form of a storage plate conductor); (ii) bi-stable three-terminal latch device using two Ecrit property regions; (iii) three-terminal, two-Ecrit-region latch device where, for each Ecrit region, (Vdd−Vss) divided by (region thickness, dn) is greater than the region's Ecrit value; or (iv) use of multiple Ecrit material region latch devices to provide data storage instrumentality in a static memory device.

Abstract translation: 本发明的一些实施例可以包括以下特征，特征或优点中的一个或多个：（i）闩锁装置，包括多个Ecrit材料区域，所述Ecrit材料区域全部电连接到公共端子（有时结构化并以存储器的形式形成 板导体）; （ii）使用两个Ecrit属性区域的双稳态三端锁存装置; （iii）三端，双E区域锁存装置，其中对于每个Ecrit区域（Vdd-Vss）除以（区域厚度dn）大于该区域的Ecrit值; 或（iv）使用多个Ecrit材料区域锁存器件来在静态存储器件中提供数据存储器具。

公开(公告)号：US20160172420A1

公开(公告)日：2016-06-16

申请号：US14567499

申请日：2014-12-11

Applicant: International Business Machines Corporation

Inventor： Mohit Bajaj ,  Geoffrey W. Burr ,  Kota V.R.M. Murali ,  Rajan K. Pandey ,  Rajesh Sathiyanarayanan ,  Kumar R. Virwani

IPC: H01L27/24 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C2213/52 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

Abstract: A device that includes a semiconductor device and a contact electrode with a first side that is opposite a second side. The first side abuts the semiconductor device. The contact electrode has a stoichiometry that varies from the first side to the second side. The stoichiometry of the first side inhibits the diffusion of metal from the semiconductor device into the first contact electrode.

Abstract translation: 一种包括半导体器件和具有与第二侧相对的第一侧的接触电极的器件。 第一面邻接半导体器件。 接触电极具有从第一侧向第二侧变化的化学计量。 第一侧的化学计量抑制金属从半导体器件扩散到第一接触电极中。

公开(公告)号：US20160133648A1

公开(公告)日：2016-05-12

申请号：US14537188

申请日：2014-11-10

Applicant: International Business Machines Corporation

Inventor： Mohit Bajaj ,  Suresh Gundapaneni ,  Aniruddha Konar ,  Kota V.R.M. Murali ,  Edward J. Nowak

IPC: H01L27/12 ,  H01L29/51 ,  H01L21/02 ,  H01L29/10 ,  H01L21/84 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/66977 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4908 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/78645 ,  H01L29/78648 ,  H01L49/003

Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a doped semiconductor layer having a substantially uniform doping profile; a first gate structure positioned on the doped semiconductor layer; and a second gate structure positioned on the doped semiconductor layer, the second gate structure including a metal-insulator transition material and a gate dielectric layer separating the metal-insulator transition material from the doped semiconductor layer.

Abstract translation: 本公开的实施例提供集成电路（IC）结构，其可以包括：具有基本上均匀的掺杂分布的掺杂半导体层; 位于所述掺杂半导体层上的第一栅极结构; 以及位于所述掺杂半导体层上的第二栅极结构，所述第二栅极结构包括金属 - 绝缘体转变材料和将所述金属 - 绝缘体转变材料与所述掺杂半导体层分离的栅极电介质层。