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    Instructions and logic for blend and permute operation sequences
    5.
    发明授权
    Instructions and logic for blend and permute operation sequences 有权

    公开(公告)号：US10152321B2

    公开(公告)日：2018-12-11

    申请号：US14974729

    申请日：2015-12-18

    Applicant: Intel Corporation

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Suleyman Sair ,  Joonmoo Huh

    IPC: G06F9/30

    Abstract: A processor includes a core to execute an instruction and logic to determine that the instruction will require strided data converted from source data in memory. The strided data is to include corresponding indexed elements from structures in the source data to be loaded into a same register to be used to execute the instruction. The core also includes logic to load source data into preliminary vector registers. The source data is to be unaligned as resident in the vector registers. The core includes logic to apply blend instructions to contents of the preliminary vector registers to cause corresponding indexed elements from the plurality of structures to be loaded into respective interim vector registers, and to apply further blend instructions to contents of the interim vector registers to cause additional indexed elements from the structures to be loaded into respective source vector registers.

    INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL MAJORITY VOTING FUNCTIONALITY
    6.
    发明申请
    INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL MAJORITY VOTING FUNCTIONALITY 审中-公开
    指令和逻辑提供向量水平主要投票功能

    公开(公告)号：US20170003962A1

    公开(公告)日：2017-01-05

    申请号：US15267668

    申请日：2016-09-16

    Applicant: Intel Corporation

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Kshitij A. Doshi ,  Suleyman Sair ,  Charles R. Yount

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F7/22 ,  G06F7/544 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F11/1048 ,  G06F11/1479

    Abstract: Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.

    Abstract translation: 指令和逻辑提供向量横向多数投票功能。 一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取一些数值，对应于指令指定的掩码，并将结果值存储到目标操作数中的相应数据字段数，从大多数 从源操作数的数据字段数读取的值。

    Providing vector horizontal compare functionality within a vector register
    7.
    发明授权
    Providing vector horizontal compare functionality within a vector register 有权

    公开(公告)号：US10318291B2

    公开(公告)日：2019-06-11

    申请号：US15585505

    申请日：2017-05-03

    Applicant: INTEL CORPORATION

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Charles R. Yount ,  Suleyman Sair ,  Kshitij A. Doshi

    IPC: G06F9/30 ,  G06F7/06

    Abstract: A processor includes a vector register including data fields to store values of vector elements of data, a decoder to decode a single instruction multiple data (SIMD) instruction specifying a source operand and a mask to identify a masked portion of the data fields. An execution unit is to read a plurality of values from unmasked data fields of the plurality of data fields of the vector register; compare, within the vector register, each of the plurality of values from the unmasked data fields for equality with all other values of the plurality of values; and responsive to a detection of an inequality of any two values of the plurality of values, set a mask field, corresponding to a detected unequal value, to a masked state with a flip of a bit value of the mask field, to signal the detection of the inequality.

    Instruction and Logic for Permute Sequence
    9.
    发明申请
    Instruction and Logic for Permute Sequence 审中-公开

    公开(公告)号：US20170177355A1

    公开(公告)日：2017-06-22

    申请号：US14975380

    申请日：2015-12-18

    Applicant: Intel Corporation

    Inventor： Elmoustapha Ould-Ahmed-Vall ,  Suleyman Sair ,  Joonmoo Huh

    IPC: G06F9/30 ,  G06F12/08

    CPC classification number: G06F9/30036 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3455 ,  G06F12/0875 ,  G06F2212/452

    Abstract: A processor includes a core to execute an instruction and logic to determine that the instruction will require strided data converted from source data in memory. The strided data is to include corresponding indexed elements from structures in the source data to be loaded into a final register to be used to execute the instruction. The core also includes logic to load source data into a plurality of preliminary vector registers to align a defined element of one of the preliminary vector registers in a position that corresponds to a required position in the final register for execution. The core includes logic to apply permute instructions to contents of the preliminary vector registers to cause corresponding indexed elements from the structures to be loaded into respective source vector registers.

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