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    Methods, apparatus, and instructions for converting vector data
    5.
    发明授权
    Methods, apparatus, and instructions for converting vector data 有权
    用于转换矢量数据的方法，装置和指令

    公开(公告)号：US09495153B2

    公开(公告)日：2016-11-15

    申请号：US13844111

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    IPC: G06F9/312 ,  G06F9/302 ,  G06F9/30

    CPC classification number: G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

    Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

    Abstract translation: 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。

    Providing extended cache replacement state information
    6.
    发明授权
    Providing extended cache replacement state information 有权
    提供扩展缓存替换状态信息

    公开(公告)号：US09170955B2

    公开(公告)日：2015-10-27

    申请号：US13685991

    申请日：2012-11-27

    Applicant: Intel Corporation

    Inventor： Andrew T. Forsyth ,  Ramacharan Sundararaman ,  Eric Sprangle ,  John C. Mejia ,  Douglas M. Carmean ,  Edward T. Grochowski ,  Robert D. Cavin

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/126 ,  G06F12/123 ,  Y02D10/13

    Abstract: In an embodiment, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first memory access instruction to a control logic. In turn, the control logic is to store the data in a first way of a first set of the cache memory and to store the replacement state indicator of the first level in a metadata field of the first way responsive to the decoded first memory access instruction. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，处理器包括解码逻辑，用于接收和解码第一存储器访问指令以将数据存储在具有第一级的替换状态指示符的高速缓冲存储器中，并将解码的第一存储器访问指令发送到控制逻辑。 反过来，控制逻辑是以第一组高速缓冲存储器的第一种方式存储数据，并且响应于解码的第一存储器访问指令将第一级的替换状态指示符存储在第一方式的元数据字段中 。 描述和要求保护其他实施例。

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