公开(公告)号：US09829965B2

公开(公告)日：2017-11-28

申请号：US14498014

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Herbert Hum ,  Eric Sprangle ,  Douglas Carmean ,  Rajesh Kumar

IPC: G06F1/24 ,  G06F9/00 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques are disclosed to control power and processing among a plurality of asymmetric cores. In one embodiment, a multi-core processor includes first and second processing cores, each including an arithmetic logic unit and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than the second processing core, wherein the first and second processing cores have different instruction sets, wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core, wherein instructions to run on the second processing core are translated to the instruction set of the second processing core by a software binary translation shell, and wherein the first and second processing cores are to concurrently execute instructions according to their own instruction sets.

公开(公告)号：US09753530B2

公开(公告)日：2017-09-05

申请号：US14498135

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Herbert Hum ,  Eric Sprangle ,  Douglas Carmean ,  Rajesh Kumar

IPC: G06F1/24 ,  G06F15/177 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

公开(公告)号：US20150074354A1

公开(公告)日：2015-03-12

申请号：US14541458

申请日：2014-11-14

Applicant: Intel Corporation

Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Andrew T. Forsyth ,  Michael Abrash

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F15/8069 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/345 ,  G06F9/383 ,  G06F12/02 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/6028

Abstract: A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

Abstract translation: 一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段， 值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为 第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。 描述和要求保护其他实施例。

公开(公告)号：US09939882B2

公开(公告)日：2018-04-10

申请号：US13954977

申请日：2013-07-31

Applicant: Intel Corporation

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F9/00 ,  G06F15/177 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.

公开(公告)号：US08754899B2

公开(公告)日：2014-06-17

申请号：US13785544

申请日：2013-03-05

Applicant: Intel Corporation

Inventor： Eric Sprangle

IPC: G06F13/00

CPC classification number: G06T1/20 ,  G06F3/0644 ,  G06F9/30043 ,  G06F9/3867 ,  G06F9/5016

Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.

Abstract translation: 增加吞吐量应用程序的内存带宽的技术。 在一个实施例中，特别是对于吞吐量应用而言，可以增加存储器带宽，而不会通过在存储器访问时钟的半周期上的一个或多个存储器存储区域之间流水线页面来增加互连轨迹或引脚数。

公开(公告)号：US10437320B2

公开(公告)日：2019-10-08

申请号：US15256050

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3293 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06F1/3206 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/3228 ,  G06F1/20 ,  G06F1/3287 ,  G06F12/0875

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

公开(公告)号：US09760162B2

公开(公告)日：2017-09-12

申请号：US14033008

申请日：2013-09-20

Applicant: Intel Corporation

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F9/00 ,  G06F1/32 ,  G06T1/20 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/20 ,  G06F12/0875

CPC classification number: G06F1/3293 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3869 ,  G06F9/461 ,  G06F9/5088 ,  G06F9/5094 ,  G06F12/0875 ,  G06F13/24 ,  G06F2209/5017 ,  G06F2212/452 ,  G06T1/20 ,  Y02B70/10 ,  Y02B70/1425 ,  Y02B70/30 ,  Y02B70/32 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

公开(公告)号：US10409360B2

公开(公告)日：2019-09-10

申请号：US15256101

申请日：2016-09-02

Applicant: Intel Corporation

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F1/24 ,  G06F1/3293 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06F1/3206 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/3228 ,  G06F1/20 ,  G06F1/3287 ,  G06F12/0875

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

公开(公告)号：US10181171B2

公开(公告)日：2019-01-15

申请号：US14085778

申请日：2013-11-20

Applicant: Intel Corporation

Inventor： Eric Sprangle ,  Matt Craighead ,  Chris Goodman ,  Belliappa Kuttanna

IPC: G06T1/00 ,  G06T1/20 ,  G06F15/00 ,  G06F15/16 ,  G06F15/167

Abstract: A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.

公开(公告)号：US10042814B2

公开(公告)日：2018-08-07

申请号：US14541458

申请日：2014-11-14

Applicant: Intel Corporation

Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Andrew T. Forsyth ,  Michael Abrash

IPC: G06F9/312 ,  G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F12/02 ,  G06F12/0875

Abstract: A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.