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公开(公告)号：US10061746B2
公开(公告)日：2018-08-28
申请号：US14498064
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Charles R. Yount
CPC classification number: G06F17/16 , G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30047 , G06F9/30101 , G06F9/30145 , G06F15/8007 , G06F15/8053 , G06F17/5009 , G06F17/5018
Abstract: A processor includes a front end to fetch an instruction. The instruction is to calculate a data point using inputs from a plurality of adjacent source data in a plurality of dimensions. The processor includes a decoder to decode the instruction. The processor also includes a core to, based on the decoded instruction, perform a plurality of tabular vector read operations to read the plurality of adjacent source data and perform a tabular vector calculation to execute the instruction. The tabular vector calculation is based upon results of performing the plurality of tabular vector read operations. The core is further to write results of the tabular vector calculation.
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公开(公告)号：US09928063B2
公开(公告)日：2018-03-27
申请号：US15267668
申请日：2016-09-16
Applicant: Intel Corporation
Inventor： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
CPC classification number: G06F9/30036 , G06F7/22 , G06F7/544 , G06F9/30018 , G06F9/30021 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F11/1048 , G06F11/1479
Abstract: Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
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公开(公告)号：US20170235572A1
公开(公告)日：2017-08-17
申请号：US15585505
申请日：2017-05-03
Applicant: INTEL CORPORATION
Inventor： Elmoustapha Ould-Ahmed-Vall , Charles R. Yount , Suleyman Sair , Kshitij A. Doshi
CPC classification number: G06F9/30018 , G06F9/30021 , G06F9/30036
Abstract: A processor includes a vector register including data fields to store values of vector elements of data, a decoder to decode a single instruction multiple data (SIMD) instruction specifying a source operand and a mask to identify a masked portion of the data fields. An execution unit is to read a plurality of values from unmasked data fields of the plurality of data fields of the vector register; compare, within the vector register, each of the plurality of values from the unmasked data fields for equality with all other values of the plurality of values; and responsive to a detection of an inequality of any two values of the plurality of values, set a mask field, corresponding to a detected unequal value, to a masked state with a flip of a bit value of the mask field, to signal the detection of the inequality.
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公开(公告)号：US10318291B2
公开(公告)日：2019-06-11
申请号：US15585505
申请日：2017-05-03
Applicant: INTEL CORPORATION
Inventor： Elmoustapha Ould-Ahmed-Vall , Charles R. Yount , Suleyman Sair , Kshitij A. Doshi
Abstract: A processor includes a vector register including data fields to store values of vector elements of data, a decoder to decode a single instruction multiple data (SIMD) instruction specifying a source operand and a mask to identify a masked portion of the data fields. An execution unit is to read a plurality of values from unmasked data fields of the plurality of data fields of the vector register; compare, within the vector register, each of the plurality of values from the unmasked data fields for equality with all other values of the plurality of values; and responsive to a detection of an inequality of any two values of the plurality of values, set a mask field, corresponding to a detected unequal value, to a masked state with a flip of a bit value of the mask field, to signal the detection of the inequality.
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公开(公告)号：US20170357514A1
公开(公告)日：2017-12-14
申请号：US15687315
申请日：2017-08-25
Applicant: Intel Corporation
Inventor： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Charles R. Yount , Suleyman Sair
CPC classification number: G06F9/3887 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30105 , G06F9/30145 , G06F9/3836 , G06F15/8061
Abstract: Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20160092400A1
公开(公告)日：2016-03-31
申请号：US14498064
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Charles R. Yount
CPC classification number: G06F17/16 , G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30047 , G06F9/30101 , G06F9/30145 , G06F15/8007 , G06F15/8053 , G06F17/5009 , G06F17/5018
Abstract: A processor includes a front end to fetch an instruction. The instruction is to calculate a data point using inputs from a plurality of adjacent source data in a plurality of dimensions. The processor includes a decoder to decode the instruction. The processor also includes a core to, based on the decoded instruction, perform a plurality of tabular vector read operations to read the plurality of adjacent source data and perform a tabular vector calculation to execute the instruction. The tabular vector calculation is based upon results of performing the plurality of tabular vector read operations. The core is further to write results of the tabular vector calculation.
Abstract translation: 一个处理器包括一个前端来取指令。 该指令是使用来自多个维度中的多个相邻源数据的输入来计算数据点。 处理器包括解码器来解码指令。 处理器还包括一个核心，用于基于解码的指令执行多个表格向量读取操作，以读取多个相邻源数据，并执行表格向量计算以执行该指令。 表格向量计算基于执行多个表格向量读取操作的结果。 核心是进一步写出表格向量计算的结果。
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7.发明授权公开(公告)号：US09971391B2
公开(公告)日：2018-05-15
申请号：US14757903
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Devadatta Bodas , Meenakshi Arunachalam , Ilya Sharapov , Charles R. Yount , Scott B. Huck , Ramakrishna Huggahalli , Justin J. Song , Brian J. Griffith , Muralidhar Rajappa , Lingdan (Linda) Zeng
CPC classification number: G06F1/3206 , G06F1/324 , G06F11/3428 , Y02D10/126
Abstract: A method of assessing energy efficiency of a High-performance computing (HPC) system, including: selecting a plurality of HPC workloads to run on a system under test (SUT) with one or more power constraints, wherein the SUT includes a plurality of HPC nodes in the HPC system, executing the plurality of HPC workloads on the SUT, and generating a benchmark metric for the SUT based on a baseline configuration for each selected HPC workload and a plurality of measured performance per power values for each executed workload at each selected power constraint is shown.
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公开(公告)号：US20170177360A1
公开(公告)日：2017-06-22
申请号：US14977445
申请日：2015-12-21
Applicant: Intel Corporation
CPC classification number: G06F9/30036 , G06F9/30101 , G06F9/3016 , G06F12/084 , G06F12/0855 , G06F12/0862 , G06F12/0875 , G06F12/1027 , G06F2212/452
Abstract: A processor includes an execution unit to execute instructions to load indices from an array of indices and scatter elements to locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be scattered by the instruction, as needed, an index value to be used in computing the address in memory at which a particular data element is to be written. The index values may be retrieved from an array of indices identified for the instruction. The execution unit includes logic to compute the addresses based on the sum of a base address specified for the instruction and the index values retrieved for the data element locations, with optional scaling. The execution unit includes logic to retrieve data elements from contiguous locations in a source vector register specified for the instruction and store them to the computed locations.
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9.发明申请INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL MAJORITY VOTING FUNCTIONALITY 审中-公开指令和逻辑提供向量水平主要投票功能公开(公告)号：US20170003962A1
公开(公告)日：2017-01-05
申请号：US15267668
申请日：2016-09-16
Applicant: Intel Corporation
Inventor： Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F7/22 , G06F7/544 , G06F9/30018 , G06F9/30021 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F11/1048 , G06F11/1479
Abstract: Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
Abstract translation: 指令和逻辑提供向量横向多数投票功能。 一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取一些数值，对应于指令指定的掩码，并将结果值存储到目标操作数中的相应数据字段数，从大多数 从源操作数的数据字段数读取的值。
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公开(公告)号：US10509726B2
公开(公告)日：2019-12-17
申请号：US14975809
申请日：2015-12-20
Applicant: Intel Corporation
IPC: G06F9/30 , G06F9/38 , G06F12/08 , G06F12/0875 , G06F12/0862 , G06F9/345 , G06F9/355 , G06F9/35
Abstract: A processor includes an execution unit to execute instructions to load indices from an array of indices, optionally perform scatters, and prefetch (to a specified cache) contents of target locations for future scatters from arbitrary locations in memory. The execution unit includes logic to load, for each target location of a scatter or prefetch operation, an index value to be used in computing the address in memory for the operation. The index value may be retrieved from an array of indices identified for the instruction. The execution unit includes logic to compute the addresses based on the sum of a base address specified for the instruction, the index value retrieved for the location, and a prefetch offset (for prefetch operations), with optional scaling. The execution unit includes logic to retrieve data elements from contiguous locations in a source vector register specified for the instruction to be scattered to the memory.
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