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    DYNAMIC DETECTION AND PREDICTION FOR STORE-DEPENDENT BRANCHES
    7.
    发明申请
    DYNAMIC DETECTION AND PREDICTION FOR STORE-DEPENDENT BRANCHES 审中-公开

    公开(公告)号：US20190220284A1

    公开(公告)日：2019-07-18

    申请号：US15870595

    申请日：2018-01-12

    Applicant: Intel Corporation

    Inventor： Saurabh Gupta ,  Rahul Pal ,  Niranjan Soundararajan ,  Ragavendra Natarajan ,  Sreenivas Subramoney

    IPC: G06F9/38

    CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/3859 ,  G06F9/3861

    Abstract: One embodiment provides an apparatus. The apparatus includes a store direct dependent (SDD) branch prediction circuitry and an SDD management circuitry. The store direct dependent (SDD) branch prediction circuitry is to store an SDD branch table. The SDD branch table is to store at least one record. Each record includes a branch instruction pointer (IP) field, a load IP field, a store IP field, a comparison info field and at least one of a store value field and/or a predicted outcome field. The SDD management circuitry is to populate the SDD branch table at runtime and to override a baseline branch prediction associated with an incoming branch IP with an SDD branch prediction, if the SDD branch table contains a first record populated with the incoming branch IP and at least one of a store value and/or an SDD predicted outcome.

    Changing cache ownership in clustered multiprocessor
    9.
    发明授权
    Changing cache ownership in clustered multiprocessor 有权

    公开(公告)号：US09690706B2

    公开(公告)日：2017-06-27

    申请号：US14668831

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

    IPC: G06F12/08 ,  G06F12/084

    CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

    Abstract: Resolving coherency issues inherent in sharing distributed cache is described. A chip multiprocessor may include at least first and second processing clusters, each having multiple cores of a processor, multiple cache slices co-located with the multiple cores, and a memory controller (MC). The processor stores directory information in a memory coupled to the processor to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space, the processor may remap first lines of first cache slices, corresponding to the first address space, to second lines in second cache slices of the second cluster, and update the directory information (e.g., a state of the first cache lines) to change the cluster cache ownership of the first address space to the second cluster. One of the MCs may manage such updating of the directory.

    Early wake-warn for clock gating control
    10.
    发明授权
    Early wake-warn for clock gating control 有权
    提前唤醒时钟门控控制

    公开(公告)号：US09552308B2

    公开(公告)日：2017-01-24

    申请号：US14126919

    申请日：2013-09-30

    Applicant: Intel Corporation

    Inventor： Suresh Sugumar ,  Mahesh K. Kumashikar ,  Rahul Pal ,  Sridhar Muthrasanallur

    IPC: G06F13/00 ,  G06F13/42 ,  G06F9/46

    CPC classification number: G06F13/00 ,  G06F1/3206 ,  G06F9/46 ,  G06F13/4273 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A request associated with a particular cache record is generated to be sent to a system component associated with a cache bank over an interconnect. A wake-warn signal is sent over a dedicated wake-warn channel to indicate to the system component that the request is to arrive. Wake-warn signals cause a disabled clock to be ungated to an enabled state. The request is then sent to the system component.

    Abstract translation: 生成与特定高速缓存记录相关联的请求，以通过互连发送到与高速缓存组相关联的系统组件。 唤醒警告信号通过专用的唤醒通道发送，以向系统组件指示请求到达。 唤醒信号导致禁用的时钟被禁止到启用状态。 然后将请求发送到系统组件。

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