公开(公告)号：US09552308B2

公开(公告)日：2017-01-24

申请号：US14126919

申请日：2013-09-30

Applicant: Intel Corporation

Inventor： Suresh Sugumar ,  Mahesh K. Kumashikar ,  Rahul Pal ,  Sridhar Muthrasanallur

IPC: G06F13/00 ,  G06F13/42 ,  G06F9/46

CPC classification number: G06F13/00 ,  G06F1/3206 ,  G06F9/46 ,  G06F13/4273 ,  Y02D10/14 ,  Y02D10/151

Abstract: A request associated with a particular cache record is generated to be sent to a system component associated with a cache bank over an interconnect. A wake-warn signal is sent over a dedicated wake-warn channel to indicate to the system component that the request is to arrive. Wake-warn signals cause a disabled clock to be ungated to an enabled state. The request is then sent to the system component.

Abstract translation: 生成与特定高速缓存记录相关联的请求，以通过互连发送到与高速缓存组相关联的系统组件。 唤醒警告信号通过专用的唤醒通道发送，以向系统组件指示请求到达。 唤醒信号导致禁用的时钟被禁止到启用状态。 然后将请求发送到系统组件。

公开(公告)号：US11675715B2

公开(公告)日：2023-06-13

申请号：US16366789

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Suresh Sugumar ,  Vishwanath Somayaji ,  Sudeep Divakaran

IPC: G06F13/16 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F13/1642 ,  G06F1/266 ,  G06F13/4282 ,  G06F2213/0042

Abstract: Methods and apparatus for implementing a low-pin count architecture with priority message arbitration and delivery. The architecture includes a hardware-based message arbitration unit (MAU) including a plurality of priority queues, each having a respective priority level, implemented on a first component, such as a processor and/or System on a Chip (SoC). The first component is communicatively coupled to a second component via a low-pin count link such as an I2C bus. The MAU receives prioritized messages from clients and enqueues the messages in priority queues based on their priority levels. An arbiter selects messages to transmit over the low-pin count link from the priority queues. The MAU further may abort transmission of a message in favor of transmission of a higher-priority message to guarantee a transmit latency. Under one implementation, the components are a processor and a PMIC configured to communicate with a USB Type-C power source and meet timing requirements defined by a USB Power Delivery Specification.

公开(公告)号：US08904205B2

公开(公告)日：2014-12-02

申请号：US14171148

申请日：2014-02-03

Applicant: Intel Corporation

Inventor： James S. Burns ,  Baskaran Ganesan ,  Russell J. Fenger ,  Devadatta V. Bodas ,  Sundaravarathan R. Iyengar ,  Feranak Nelson ,  John M. Powell, Jr. ,  Suresh Sugumar

IPC: G06F1/00 ,  G06F9/46 ,  G06F1/26 ,  G06F9/50 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

公开(公告)号：US08683240B2

公开(公告)日：2014-03-25

申请号：US13780038

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： James S. Burns ,  Baskaran Ganesan ,  Russell J. Fenger ,  Devadatta V. Bodas ,  Sundaravarathan R. Iyengar ,  Feranak Nelson ,  John M. Powell, Jr. ,  Suresh Sugumar

IPC: G06F1/00 ,  G06F9/46

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器具有多个核来执行线程。 处理器还包括功率控制逻辑，用于基于存储核心功率计数的计数器的阈值和识别至少一个线程的turbo模式请求的性能组合之间的比较来进入turbo模式。 以这种方式，可以在提供高功率效率的处理器的利用水平上输入turbo模式。 描述和要求保护其他实施例。