公开(公告)号：US12197374B2

公开(公告)日：2025-01-14

申请号：US17359321

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Nayan Amrutlal Suthar ,  David M. Puffer ,  Ashok Jagannathan

IPC: G06F13/42 ,  G06F12/0815 ,  G06T1/20

Abstract: A processor unit comprising a first controller to couple to a host processing unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host central processing unit via a third link; and circuitry to determine whether to send a cache coherent request to the host central processing unit over the first link or over the second link via the second processing unit.

公开(公告)号：US20210318980A1

公开(公告)日：2021-10-14

申请号：US17359321

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Nayan Amrutlal Suthar ,  David M. Puffer ,  Ashok Jagannathan

IPC: G06F13/42 ,  G06F12/0815 ,  G06T1/20

Abstract: A processor unit comprising a first controller to couple to a host processing unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host central processing unit via a third link; and circuitry to determine whether to send a cache coherent request to the host central processing unit over the first link or over the second link via the second processing unit.