公开(公告)号：US20190067493A1

公开(公告)日：2019-02-28

申请号：US15693392

申请日：2017-08-31

申请人： IXYS, LLC

发明人： Kyoung Wook Seok

IPC分类号： H01L29/861 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/8611 ,  H01L23/3171 ,  H01L29/0603 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/66098 ,  H01L29/66136 ,  H01L29/861

摘要： An inverse diode die is “fast” (i.e., has a small peak reverse recovery current) due to the presence of a novel topside P+ type charge carrier extraction region and a lightly-doped bottomside transparent anode. During forward conduction, the number of charge carriers in the N-type drift region is reduced due to holes being continuously extracted by an electric field set up by the P+ type charge carrier extraction region. Electrons are extracted by the transparent anode. When the voltage across the device is then reversed, the magnitude of the peak reverse recovery current is reduced due to there being a smaller number of charge carriers that need to be removed before the diode can begin reverse blocking mode operation. Advantageously, the diode is fast without having to include lifetime killers or otherwise introduce recombination centers. The inverse diode therefore has a desirably small reverse leakage current.

公开(公告)号：US20180342608A1

公开(公告)日：2018-11-29

申请号：US16035566

申请日：2018-07-13

申请人： IXYS, LLC

发明人： Kyoung Wook Seok

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L23/482 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535

摘要： Stripe-shaped surface transistor structures of a power MOSFET are disposed over an array of parallel-extending P type Buried Stripe-Shaped Charge Compensation Regions (BSSCCRs). The power MOSFET has two and only two epitaxial semiconductor layers, and the BSSCCRs are disposed at the interface between these layers. Looping around the area occupied by these parallel-extending BSSCCRs is a P type ring-shaped BSSCCR. At the upper semiconductor surface are disposed three P type surface rings. The inner surface ring and outer surface ring are coupled together by a bridging metal member, but the center surface ring is floating. The bridging metal member is disposed at least in part over the ring-shaped BSSCCR. The MOSFET has a high breakdown voltage, a low RDS(ON), and is acceptable and suitable for manufacture at semiconductor fabrication. plants that cannot or typically do not make superjunction MOSFETs.

公开(公告)号：US10319669B2

公开(公告)日：2019-06-11

申请号：US15693416

申请日：2017-08-31

申请人： IXYS, LLC

发明人： Kyoung Wook Seok

IPC分类号： H01L23/495 ,  H01L23/31 ,  H02M1/42 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/861 ,  H01L29/51 ,  H01L29/49 ,  H01L29/45 ,  H01L29/167

摘要： A novel four-terminal packaged semiconductor device is particularly useful in a 400 volt DC output PFC boost converter circuit. Within the body of the package an NFET die and a fast inverse diode die are mounted such that a bottomside drain electrode of the NFET is electrically coupled via a die attach tab to a bottomside P type anode region of the inverse diode. First terminal T1 is coupled the die attach tab. Second terminal T2 is coupled to the gate of the NFET die. Third terminal T3 is coupled to the source of the NFET die. Fourth terminal T4 is coupled to a topside cathode electrode of the fast inverse diode die. Due to a novel P+ type charge carrier extraction region of the inverse diode die, the packaged device is fast and has a low reverse leakage current in the PFC boost converter circuit application.

公开(公告)号：US20190067174A1

公开(公告)日：2019-02-28

申请号：US15693416

申请日：2017-08-31

申请人： IXYS, LLC

发明人： Kyoung Wook Seok

IPC分类号： H01L23/495 ,  H01L23/31 ,  H02M1/42

摘要： A novel four-terminal packaged semiconductor device is particularly useful in a 400 volt DC output PFC boost converter circuit. Within the body of the package an NFET die and a fast inverse diode die are mounted such that a bottomside drain electrode of the NFET is electrically coupled via a die attach tab to a bottomside P type anode region of the inverse diode. First terminal T1 is coupled the die attach tab. Second terminal T2 is coupled to the gate of the NFET die. Third terminal T3 is coupled to the source of the NFET die. Fourth terminal T4 is coupled to a topside cathode electrode of the fast inverse diode die. Due to a novel P+ type charge carrier extraction region of the inverse diode die, the packaged device is fast and has a low reverse leakage current in the PFC boost converter circuit application.

公开(公告)号：US10014852B2

公开(公告)日：2018-07-03

申请号：US15421405

申请日：2017-01-31

申请人： IXYS, LLC

发明人： Kyoung Wook Seok

IPC分类号： H03K3/00 ,  H03K17/10

CPC分类号： H03K17/107 ,  H03K17/08122 ,  H03K17/102

摘要： A High-Voltage Stacked Transistor Circuit (HVSTC) includes a stack of power transistors coupled in series between a first terminal and a second terminal. The HVSTC also has a control terminal for turning on an off the power transistors of the stack. All of the power transistors of the stack turn on together, and turn off together, so that the overall stack operates like a single transistor having a higher breakdown voltage. Each power transistor, other than the one most directly coupled to the first terminal, has an associated bipolar transistor. In a static on state of the HVSTC, the bipolar transistors are off. The associated power transistors can therefore be turned on. In a static off state of the HVSTC, the bipolar transistors are conductive (in one example, in the reverse active mode) in such a way that they keep their associated power transistors off.

公开(公告)号：US10249716B1

公开(公告)日：2019-04-02

申请号：US15698556

申请日：2017-09-07

申请人： IXYS, LLC

发明人： Kyoung Wook Seok ,  Joseph James Roosma

IPC分类号： H01L29/66 ,  H01L29/10

摘要： A combination switch includes an Insulated Gate Bipolar Transistor (IGBT), an anti-parallel diode, and a saturable inductor. The diode and inductor are coupled in series between a collector and an emitter of the IGBT. The inductor is fashioned so that it will come out of saturation when a forward bias current flow through the diode falls below a saturation current level. When the diode current falls (for example, due to another combination switch of a phase leg turning on), the diode current initially falls at a high rate until the inductor current drops to the saturation current level. Thereafter, the diode current falls at a lower rate. The lower rate allows the diode current to have a soft landing to zero current, thereby eliminating or reducing voltage and/or current spikes that would otherwise occur. Multiple methods of implementing and manufacturing the saturable inductor are disclosed.