公开(公告)号：US20170373160A1

公开(公告)日：2017-12-28

申请号：US15193404

申请日：2016-06-27

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： KANGGUO CHENG ,  XIN MIAO ,  WENYU XU ,  CHEN ZHANG

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： A method for forming a semiconductor device comprises forming a sacrificial gate stack on a substrate, spacers adjacent to the sacrificial gate stack, and a source/drain region on the substrate. A first insulator layer is formed on the source/drain region. A portion of the first insulator layer is removed to expose portions of the spacers. Exposed sidewall portions of the spacers are removed to reduce a thickness of the exposed portions of the spacers. A protective layer is deposited over the exposed sidewalls of the spacers and a second insulator layer is deposited over the protective layer. The sacrificial gate is removed to expose a channel region of the substrate. A gate stack is formed over the channel region of the substrate. Exposed portions of the first insulator layer and the second insulator layer are removed to expose the source/drain region, and a conductive is formed on the source/drain region.

公开(公告)号：US20200176558A1

公开(公告)日：2020-06-04

申请号：US16785743

申请日：2020-02-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： KANGGUO CHENG ,  XIN MIAO ,  WENYU XU ,  CHEN ZHANG

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/786 ,  H01L27/088

摘要： A method of forming a semiconductor structure is provided. Trenches are formed in a first dielectric layer having a first height on a substrate. First III-V semiconductor patterns including aluminum are formed in the trenches to a second height lower than the first height. Second III-V semiconductor patterns are formed on the first III-V semiconductor patterns to a third height not higher than the first height to form fins including the first and second III-V semiconductor patterns. The first dielectric layer is completely removed to expose the fins. Selective oxidation is performed to oxidize the first III-V semiconductor patterns to form oxidized first III-V semiconductor patterns. Fin patterning is performed. A second dielectric layer is formed to cover the fins. The second dielectric layer is recessed to a level not higher than top surfaces of the oxidized first III-V semiconductor patterns. The semiconductor structure is also provided.

公开(公告)号：US20180005895A1

公开(公告)日：2018-01-04

申请号：US15196774

申请日：2016-06-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： KANGGUO CHENG ,  XIN MIAO ,  WENYU XU ,  CHEN ZHANG

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/823456 ,  H01L21/02636 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

摘要： A method of forming a vertical transistor includes forming a first pair of fins on a substrate; forming a second pair of fins on the substrate; forming a first trench in the substrate and interposed between each one of the first pair of fins; forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench; forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region; and forming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region.

公开(公告)号：US20230101011A1

公开(公告)日：2023-03-30

申请号：US17448777

申请日：2021-09-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： RUILONG XIE ,  WENYU XU ,  INDIRA SESHADRI ,  JING GUO ,  EKMINI ANUJA DE SILVA

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40

摘要： A semiconductor device is provided. The semiconductor device includes a bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer, the gate stack including a work function metal (WFM) layer, a channel fin formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed in a gate landing area over the gate stack, a second ILD layer formed in an area other than the gate landing area, and a WFM encapsulation layer formed between the first ILD layer and the second ILD layer, and formed on sidewalls of the gate stack.