公开(公告)号：US20040051178A1

公开(公告)日：2004-03-18

申请号：US10661328

申请日：2003-09-12

Applicant: International Business Machines Corporation

Inventor： Stephen Alan Cohen ,  Timothy Joseph Dalton ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Brian Wayne Herbst ,  Sampath Purushothaman ,  Stanley Joseph Whitehair

IPC: H01L023/48

CPC classification number: H01L21/76829 ,  H01L21/76804 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position about 2-5 nanometers below a, to be planarized, surface where there will be a lower electric field. The invention is particularly useful in the damascene type device structure in the art wherein adjacent conductors extend from a substrate through an interlevel dielectric material, connections are made in a trench, a diffusion barrier liner is provided in the interlevel dilectric material and masking is employed to protect the dilectric material between conductors during processing operations.

Abstract translation: 为半导体器件提供金属加上低介电常数（低k）互连结构，其中由电介质隔开的表面中的相邻区域在亚250纳米范围内具有宽度和间距的尺寸，并且其中减小横向漏电流 相邻的金属线和比常规结构更低的有效介电常数是通过在后续处理操作中在约2-5纳米以下的位置处定位用于保护电介质的微分或掩模构件来实现的 ，要平坦化，会有较低电场的表面。 本发明特别适用于本领域的镶嵌型器件结构，其中相邻导体从衬底延伸通过层间电介质材料，在沟槽中形成连接，在层间电介质材料中提供扩散阻挡衬垫，并且使用掩模 在处理操作期间保护导体之间的电介质材料。

公开(公告)号：US20030162047A1

公开(公告)日：2003-08-28

申请号：US10375333

申请日：2003-02-27

Applicant: International Business Machines Corporation

Inventor： Bernd K. Appelt ,  Jeffrey D. Gelorme ,  Sung Kwon Kang ,  Voya R. Markovich ,  Kostas Papathomas ,  Sampath Purushothaman

IPC: B32B001/00

CPC classification number: H01L23/49827 ,  H01B1/02 ,  H01B1/22 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/095 ,  H05K3/4069 ,  Y10T428/12181 ,  Y10T428/2991 ,  Y10T428/2993 ,  Y10T428/2998 ,  H01L2924/00

Abstract: The present invention provides a unique conductive composition for filling vias or through holes to make reliable vertical or Z-connects. The through holes may be plated or unplated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.

Abstract translation: 本发明提供了用于填充通孔或通孔以形成可靠的垂直或Z形连接的独特导电组合物。 在填充之前可以对通孔进行电镀或未镀层。 还公开了使用该特征制造高密度电子封装的描述。

公开(公告)号：US20030136813A1

公开(公告)日：2003-07-24

申请号：US10052619

申请日：2002-01-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John Harold Magerlein ,  Samuel Roy McKnight ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Joseph J. Van Horn ,  Richard Paul Volant ,  George Frederick Walker

IPC: B23K031/12 ,  B23K031/02

CPC classification number: H01L24/11 ,  G01R1/0416 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/325 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: A system for testing a collection of device chips by temporarily attaching them to a carrier having a plurality of receptacles with microdendritic features; the receptacles matching with and pushed in contact with a matching set of contact pads on the device chips; said carrier additionally having test pads connected to the receptacles through interconnect wiring. The system allows connecting the chips together and testing the collection as a whole by probing the test pads on the carrier. Burn-in of the collection of chips can also be performed on the temporary carrier, which is reusable.

Abstract translation: 一种用于通过将装置芯片临时附接到具有多个具有微树突状特征的容器的载体来测试装置芯片集合的系统; 所述插座与所述器件芯片上的匹配的接触焊盘组匹配并且与所述插座接触; 所述载体另外具有通过互连布线连接到插座的测试垫。 该系统允许将芯片连接在一起，并通过探测载体上的测试垫来整体测试集合。 芯片集合的老化也可以在临时载体上执行，这是可重复使用的。

公开(公告)号：US20040150096A1

公开(公告)日：2004-08-05

申请号：US10645047

申请日：2003-08-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sampath Purushothaman ,  Anna W. Topol

IPC: H01L023/14

CPC classification number: H01L21/0217 ,  H01L21/02126 ,  H01L21/02266 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3164 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/45147 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2224/48

Abstract: A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

Abstract translation: 提供一种用于半导体部件的结构，其具有集成并构建在待传送的支撑层上的双层封盖涂层。 双层封盖保护层免受由用于层转移的载体组件的附接和移除过程所导致的可能的劣化的转移。 使用该结构的晶片级层传送处理能够创建三维集成电路。

公开(公告)号：US20040087176A1

公开(公告)日：2004-05-06

申请号：US10287905

申请日：2002-11-05

Applicant: International Business Machines Corporation

Inventor： Matthew E. Colburn ,  Stephen M. Gates ,  Jeffrey C. Hedrick ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian

IPC: H01L021/31

CPC classification number: H05K3/0079 ,  H01L21/0331 ,  H01L21/76849 ,  H05K3/282 ,  H05K2203/1173 ,  Y10T428/24802

Abstract: A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.

Abstract translation: 一种用于在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩蔽材料的溶液的涂层，所述掩模材料对现有图案的部分具有亲和力; 并且允许掩模材料的至少一部分优先组装到现有图案的部分。 该图案可以由具有第一原子组成的衬底的第一组区域和第二组衬底的区域组成，其具有不同于第一组成的第二原子组成。 第一组区域可以包括一个或多个金属元件，并且第二组区域可以包括电介质。 可以将第一和第二区域处理成具有不同的表面性质。 按照该方法制造的结构。 用于练习该方法的组合物。

公开(公告)号：US20030183937A1

公开(公告)日：2003-10-02

申请号：US10396274

申请日：2003-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Cristy Sensenich Tyberg

IPC: H01L047/02

CPC classification number: H01L21/76835 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low-k dielectric metal conductor interconnect structure having no micro-trenches present therein and a method of forming such a structure are provided. Specifically, the above structure is achieved by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.

公开(公告)号：US20020172811A1

公开(公告)日：2002-11-21

申请号：US09858687

申请日：2001-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Edward Paul Barth ,  Stephan A. Cohen ,  Chester Dziobkowski ,  John Anthony Fitzsimmons ,  Stephen McConnell Gates ,  Thomas Henry Ivers ,  Sampath Purushothaman ,  Darryl D. Restaino ,  Horatio Seymour Wildman

IPC: B32B009/00 ,  B32B015/00

CPC classification number: H01L21/76832 ,  B32B27/08 ,  H01L21/76834 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/24917 ,  Y10T428/31663 ,  Y10T428/31681 ,  Y10T428/31696 ,  H01L2924/00

Abstract: A diffusion barrier that has a low dielectric constant, k, yet resistant to oxygen and/or moisture permeability is provided. The diffusion barrier includes a dielectric stack having at least two or more dielectric films, each film having a dielectric constant of about 8 or less, wherein the dielectric stack comprises alternating films composed of a high-permeability material and a low-permeability material. A semiconductor structure including substrate having at least one wiring region and the inventive diffusion barrier formed on a surface of the substrate is also provided.

Abstract translation: 提供了具有低介电常数k但仍具有耐氧和/或透湿性的扩散阻挡层。 扩散阻挡层包括具有至少两个或更多个介电膜的电介质堆叠，每个膜具有约8或更小的介电常数，其中该电介质叠层包括由高导磁率材料和低导磁率材料构成的交替膜。 还提供了包括具有形成在基板的表面上的至少一个布线区域和本发明的扩散阻挡层的基板的半导体结构。

公开(公告)号：US20040087177A1

公开(公告)日：2004-05-06

申请号：US10421355

申请日：2003-04-24

Applicant: International Business Machines Corporation

Inventor： Matthew E. Colburn ,  Stephen M. Gates ,  Jeffrey C. Hedrick ,  Elbert Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian

IPC: H01L021/31 ,  H01L021/469

CPC classification number: H01L21/76849 ,  B82Y30/00 ,  G03F7/165 ,  H01L21/0331 ,  H01L21/31058 ,  H05K3/0079 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of the masking material to the substrate; and allowing at least a portion of the masking material to preferentially attach to portions of the existing pattern. The pattern is comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The masking material may comprise a polymer containing a reactive grafting site that selectively binds to the portions of the pattern. The masking material may include a polymer that binds to the portions of the pattern to provide a layer of functional groups suitable for polymerization initiation, a reactive molecule having functional groups suitable for polymerization propagation, or a reactive molecule, wherein reaction of the reactive molecule with the portion of the pattern generates a layer having reactive groups, which participate in step growth polymerization. Structures in accordance with the method. Compositions for practicing the method.

Abstract translation: 一种用于在衬底上的现有图案上形成自对准图案的方法，包括将掩模材料的涂层施加到衬底上; 并且允许掩模材料的至少一部分优先地附着到现有图案的部分上。 该图案由具有第一原子组成的基底的第一组区域和具有不同于第一组成的第二原子组成的基底的第二组区域组成。 第一组区域可以包括一个或多个金属元件，并且第二组区域可以包括电介质。 掩模材料可以包含含有选择性结合图案部分的反应性接枝位点的聚合物。 掩蔽材料可以包括聚合物，其结合图案的部分以提供适于聚合起始的官能团层，具有适用于聚合扩展的官能团的反应性分子或反应性分子，其中反应性分子与 图案的部分产生具有反应性基团的层，其参与步骤生长聚合。 结构按照方法。 组合练习方法。

公开(公告)号：US20030137058A1

公开(公告)日：2003-07-24

申请号：US10052620

申请日：2002-01-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John Harold Magerlein ,  Kevin Shawn Petrarca ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  Richard Paul Volant ,  George Frederick Walker

IPC: H01L023/48

CPC classification number: H01L24/10 ,  H01L21/67144 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/34 ,  H05K3/3436 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2201/09509 ,  H01L2924/00

Abstract: A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

公开(公告)号：US20020145200A1

公开(公告)日：2002-10-10

申请号：US09827160

申请日：2001-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy Joseph Dalton ,  Stephen McConnell Gates ,  Jeffrey Curtis Hedrick ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Christy Sensenich Tyberg

IPC: H01L021/44 ,  H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L21/76835 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.

Abstract translation: 提供了一种用作Cu互连结构的CMP后盖的旋涂帽。 本发明的旋涂帽包括低k电介质（约3.5或更小）和至少一种添加剂。 本发明中使用的至少一种添加剂能够结合Cu离子，并且可溶于旋转的低k电介质。 本发明的旋涂帽还可以包括旋转低k（约3.5或更小）反应离子蚀刻（RIE）停止层。 包含低电介质加上至少添加和低k RIE停止层的双层的旋转盖是优选的。 注意，本发明的本发明的旋涂帽不会显着增加互连结构的有效介电常数，并且不会增加互连结构的制造的额外成本，因为单个沉积工具，即旋涂工具 ，被雇用。 此外，由于在旋涂帽中存在添加剂，所以Cu迁移基本上被最小化。