公开(公告)号：US20230282722A1

公开(公告)日：2023-09-07

申请号：US17653468

申请日：2022-03-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Julien Frougier ,  Sagarika Mukesh ,  Albert M Chu ,  Ruilong Xie ,  Andrew M. Greene ,  Eric Miller ,  Junli Wang ,  Veeraraghavan S. Basker ,  Prateek Hundekar ,  Tushar Gupta ,  Su Chen Fan

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L23/48 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L23/481 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device including a first nanodevice is located on a substrate, where the first nanodevice includes at least one channel. A first source/drain connected to the first nanodevice. A second nanodevice located on the substrate, where the second nanodevice includes at least one channel and a second source/drain connected to the second nanodevice. A first contact located above the first source/drain. A second contact located above the second source/drain. A contact cap located on top of the first contact and the second contact, where the contact cap has a first leg that extends downwards between the first contact and the second contact. The first leg of the contact cap is in contact with a first sidewall of the first contact, and a first sidewall of the second contact.

公开(公告)号：US20250096074A1

公开(公告)日：2025-03-20

申请号：US18468729

申请日：2023-09-17

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Albert M Chu ,  Brent A. Anderson ,  Lawrence A. Clevenger

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a front-end-of-line (FEOL) including a first source/drain (S/D) adjacent to a first gate. A device may include a backside interconnect below the FEOL, with a plurality of signal lines and a plurality of power lines. A device may include an offset gate contact electrically connected between the first gate and a first signal line of the plurality of signal lines, wherein the offset gate contact is located directly below the first S/D.

公开(公告)号：US20230317611A1

公开(公告)日：2023-10-05

申请号：US17657378

申请日：2022-03-31

Applicant: International Business Machines Corporation

Inventor： Albert M Chu ,  Junli Wang ,  Albert M. Young ,  Dechao Guo

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L23/5286 ,  H01L27/0922 ,  H01L21/823878 ,  H01L21/823871

Abstract: Embodiments are disclosed for a system. The system includes multiple tracks. Further, one track includes a power rail for a first voltage. The system also includes a first via, disposed beneath, and in electrical contact with, the power rail. The system additionally includes a first contact, beneath, and in electrical contact with, the first via. The system further includes a first field effect transistor (FET), beneath, and in electrical isolation with, the first contact. Additionally, the system includes a second FET, beneath, and in electrical contact with, the first FET. Further, the system includes a second contact, beneath, and in electrical contact with, the second FET. Also, the system includes a second via, beneath, and in electrical contact with, the second contact. The system additionally includes a buried power rail (BPR), beneath, and in electrical contact with, the second via, wherein the BPR comprises a second voltage.

公开(公告)号：US20230320055A1

公开(公告)日：2023-10-05

申请号：US17657446

申请日：2022-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A Anderson ,  Albert M Chu ,  Junli Wang ,  Hemanth Jagannathan

IPC: H01L27/11 ,  G11C11/408

CPC classification number: H01L27/1104 ,  H01L27/1116 ,  G11C11/4085

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.

公开(公告)号：US12295133B2

公开(公告)日：2025-05-06

申请号：US17660431

申请日：2022-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Albert M Chu ,  Carl Radens ,  Kisik Choi

IPC: H10B10/00 ,  H10D30/67

Abstract: Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

公开(公告)号：US12278184B2

公开(公告)日：2025-04-15

申请号：US17657378

申请日：2022-03-31

Applicant: International Business Machines Corporation

Inventor： Albert M Chu ,  Junli Wang ,  Albert M. Young ,  Dechao Guo

IPC: H10D84/03 ,  H01L23/528 ,  H10D84/01 ,  H10D84/85

Abstract: Embodiments are disclosed for a system. The system includes multiple tracks. Further, one track includes a power rail for a first voltage. The system also includes a first via, disposed beneath, and in electrical contact with, the power rail. The system additionally includes a first contact, beneath, and in electrical contact with, the first via. The system further includes a first field effect transistor (FET), beneath, and in electrical isolation with, the first contact. Additionally, the system includes a second FET, beneath, and in electrical contact with, the first FET. Further, the system includes a second contact, beneath, and in electrical contact with, the second FET. Also, the system includes a second via, beneath, and in electrical contact with, the second contact. The system additionally includes a buried power rail (BPR), beneath, and in electrical contact with, the second via, wherein the BPR comprises a second voltage.

公开(公告)号：US20230345691A1

公开(公告)日：2023-10-26

申请号：US17660431

申请日：2022-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Albert M Chu ,  Carl Radens ,  Kisik Choi

IPC: H01L27/11 ,  H01L29/417

CPC classification number: H01L27/1108 ,  H01L29/41733

Abstract: Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

公开(公告)号：US20230343821A1

公开(公告)日：2023-10-26

申请号：US17728116

申请日：2022-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Heng Wu ,  Albert M. Young ,  Albert M Chu ,  Junli Wang ,  Brent A Anderson

IPC: H01L29/06 ,  H01L25/11

CPC classification number: H01L29/0665 ,  H01L25/117

Abstract: A semiconductor device including a first pair of stacked transistors comprising a first upper transistor and a first lower transistor, a third transistor disposed adjacent to the first lower transistor, the third transistor comprising a gate portion extending from the third transistor gate toward the first pair of stacked transistors, a cross-connection disposed in contact with the gate portion and extending upward, and a gate contact disposed in contact with the cross-connection and a top surface of the first upper transistor.