公开(公告)号：US20230320055A1

公开(公告)日：2023-10-05

申请号：US17657446

申请日：2022-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A Anderson ,  Albert M Chu ,  Junli Wang ,  Hemanth Jagannathan

IPC: H01L27/11 ,  G11C11/408

CPC classification number: H01L27/1104 ,  H01L27/1116 ,  G11C11/4085

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.

公开(公告)号：US20230307453A1

公开(公告)日：2023-09-28

申请号：US17701015

申请日：2022-03-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A Anderson ,  Junli Wang ,  Albert Chu

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/1029 ,  H01L21/823807 ,  H01L21/823871

Abstract: A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (Weff) Z, then the second logic cell has a height 2X, a width Y, and Weff>2.5 Z.

公开(公告)号：US12268026B2

公开(公告)日：2025-04-01

申请号：US17657006

申请日：2022-03-29

Applicant: International Business Machines Corporation

Inventor： Junli Wang ,  Brent A Anderson ,  Terence Hook ,  Indira Seshadri ,  Albert M. Young ,  Stuart Sieg ,  Su Chen Fan ,  Shogo Mochizuki

IPC: H10D64/23 ,  H10D64/01

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

公开(公告)号：US12268016B2

公开(公告)日：2025-04-01

申请号：US17564571

申请日：2021-12-29

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Junli Wang ,  Brent A Anderson ,  Chen Zhang ,  Heng Wu ,  Alexander Reznicek

IPC: H10D30/62 ,  H01L23/522 ,  H01L23/528 ,  H10D64/01

Abstract: A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.

公开(公告)号：US20230317802A1

公开(公告)日：2023-10-05

申请号：US17657006

申请日：2022-03-29

Applicant: International Business Machines Corporation

Inventor： Junli Wang ,  Brent A Anderson ,  Terence Hook ,  Indira Seshadri ,  Albert M. Young ,  Stuart Sieg ,  Su Chen Fan ,  Shogo Mochizuki

IPC: H01L29/417 ,  H01L29/40

CPC classification number: H01L29/41725 ,  H01L29/401

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

公开(公告)号：US20230343821A1

公开(公告)日：2023-10-26

申请号：US17728116

申请日：2022-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Heng Wu ,  Albert M. Young ,  Albert M Chu ,  Junli Wang ,  Brent A Anderson

IPC: H01L29/06 ,  H01L25/11

CPC classification number: H01L29/0665 ,  H01L25/117

Abstract: A semiconductor device including a first pair of stacked transistors comprising a first upper transistor and a first lower transistor, a third transistor disposed adjacent to the first lower transistor, the third transistor comprising a gate portion extending from the third transistor gate toward the first pair of stacked transistors, a cross-connection disposed in contact with the gate portion and extending upward, and a gate contact disposed in contact with the cross-connection and a top surface of the first upper transistor.

公开(公告)号：US20230215767A1

公开(公告)日：2023-07-06

申请号：US17565661

申请日：2021-12-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Brent A Anderson ,  Lawrence A. Clevenger ,  John Christopher Arnold

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L23/535 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/823475 ,  H01L21/76895 ,  H01L21/823885 ,  H01L23/481 ,  H01L23/535 ,  H01L27/092 ,  H01L29/66666 ,  H01L29/0673

Abstract: A semiconductor structure includes a field effect transistor (FET) including a first source-drain region, a second source-drain region, a gate between the first and second source-drain regions, and a channel region under the gate and between the first and second source-drain regions. Also included are a front side wiring network, having a plurality of front side wires, on a front side of the field effect transistor; a front side conductive path electrically interconnecting one of the front side wires with the first source-drain region; a back side power rail, on a back side of the FET; and a back side contact electrically interconnecting the back side power rail with the second source-drain region. A dielectric liner and back side dielectric fill are on a back side of the gate adjacent the back side contact, and they electrically confine the back side contact in a cross-gate direction.