公开(公告)号：US20210149680A1

公开(公告)日：2021-05-20

申请号：US17095585

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. APPU

IPC: G06F9/38 ,  G06F12/084 ,  G06F9/54 ,  G06F9/50 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20200310883A1

公开(公告)日：2020-10-01

申请号：US16367056

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： James VALERIO ,  Vasanth RANGANATHAN ,  Joydeep RAY ,  Rahul A. KULKARNI ,  Abhishek R. APPU ,  Jeffery S. BOLES ,  Hema C. NALLURI

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06T1/20

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

公开(公告)号：US20250053452A1

公开(公告)日：2025-02-13

申请号：US18774583

申请日：2024-07-16

Applicant: Intel Corporation

Inventor： Pawel MAJEWSKI ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Joshua BARCZAK ,  Vasanth RANGANATHAN ,  Vikranth VEMULAPALLI

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54

Abstract: Apparatus and method for stack access throttling for synchronous ray tracing. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations to ensure that a size of the active ray tracing stack allocations remains within a threshold; and an execution unit to execute a thread to explicitly request a new ray tracing stack allocation from the ray tracing acceleration hardware, the ray tracing acceleration hardware to permit the new ray tracing stack allocation if the size of the active ray tracing stack allocations will remain within the threshold after permitting the new ray tracing stack allocation.

公开(公告)号：US20230297419A1

公开(公告)日：2023-09-21

申请号：US17699992

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Abhishek R. APPU ,  Joydeep RAY ,  Karthik VAIDYANATHAN ,  Sreedhar CHALASANI ,  Vasanth RANGANATHAN

IPC: G06F9/48 ,  G06F9/50 ,  G06F12/0891

CPC classification number: G06F9/4881 ,  G06F9/505 ,  G06F9/5016 ,  G06F12/0891

Abstract: Bank aware thread scheduling and early dependency clearing techniques are described herein. In one example, bank aware thread scheduling involves arbitrating and scheduling threads based on the cache bank that is to be accessed by the instructions to avoiding bank conflicts. Early dependency clearing involves clearing dependencies for cache loads in a scoreboard before the data is loaded. In early dependency clearing for loads, delays in operation can be reduced by clearing dependencies before data is required from the cache.

公开(公告)号：US20250103343A1

公开(公告)日：2025-03-27

申请号：US18955259

申请日：2024-11-21

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/54 ,  G06F12/084 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20230359499A1

公开(公告)日：2023-11-09

申请号：US18195230

申请日：2023-05-09

Applicant: Intel Corporation

Inventor： James VALERIO ,  Vasanth RANGANATHAN ,  Joydeep RAY ,  Rahul A. KULKARNI ,  Abhishek R. APPU ,  Jeffery S. BOLES ,  Hema C. NALLURI

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20 ,  G06F9/38

CPC classification number: G06F9/5038 ,  G06F9/4881 ,  G06T1/20 ,  G06F9/3822 ,  G06F9/3867 ,  G06F9/5066

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

公开(公告)号：US20240184739A1

公开(公告)日：2024-06-06

申请号：US18432859

申请日：2024-02-05

Applicant: INTEL CORPORATION

Inventor： Joydeep RAY ,  Niranjan COORAY ,  Subramaniam MAIYURAN ,  Altug KOKER ,  Prasoonkumar SURTI ,  Varghese GEORGE ,  Valentin ANDREI ,  Abhishek APPU ,  Guadalupe GARCIA ,  Pattabhiraman K ,  Sungye KIM ,  Sanjay KUMAR ,  Pratik MAROLIA ,  Elmoustapha OULD-AHMED-VALL ,  Vasanth RANGANATHAN ,  William SADLER ,  Lakshminarayanan STRIRAMASSARMA

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20230418617A1

公开(公告)日：2023-12-28

申请号：US18339454

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F12/084 ,  G06T1/60 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/3891 ,  G06F12/084 ,  G06T1/60 ,  G06F9/5066 ,  G06F9/544

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20220129323A1

公开(公告)日：2022-04-28

申请号：US17339184

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： James VALERIO ,  Vasanth RANGANATHAN ,  Joydeep RAY ,  Rahul A. KULKARNI ,  Abhishek R. APPU ,  Jeffery S. BOLES ,  Hema C. NALLURI

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20 ,  G06F9/38

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.