公开(公告)号：US20240354108A1

公开(公告)日：2024-10-24

申请号：US18478882

申请日：2023-09-29

申请人： Intel Corporation

发明人： Michael LeMay ,  David M. Durham ,  Joseph Cihula ,  Joseph Nuzman ,  Dan Baum ,  Jonathan Combs

IPC分类号： G06F9/30

CPC分类号： G06F9/3016

摘要： Techniques for implementing instructions and modified instruction encodings for checking tags and for interspersing islands of tags in line with bucketed data for locality by a processor are described. In an example, an apparatus includes decoder circuitry and execution circuitry. The decoder circuitry is to decode an instruction into a decoded instruction. The instruction has an opcode to indicate that the execution circuitry is to use metadata and instruction encodings to selectively perform a memory safety check. The execution circuitry is to execute the decoded instruction according to the opcode.

公开(公告)号：US20230315630A1

公开(公告)日：2023-10-05

申请号：US17708435

申请日：2022-03-30

申请人： Intel Corporation

发明人： Hanna Alam ,  Yuval Bustan ,  Tomer Exterman ,  Dor Kahana ,  Larisa Novakovsky ,  Joseph Nuzman

IPC分类号： G06F12/0811

CPC分类号： G06F12/0811 ,  G06F2212/62

摘要： Methods and apparatus relating to a dynamic inclusive and non-inclusive caching policy are described. In an embodiment, a first cache has a higher level than a second cache. Circuitry determines a caching policy between the first cache and the second cache based on a comparison of a number of active processor cores and a threshold value. The caching policy is one of an inclusive caching policy or a non-inclusive caching policy. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220207154A1

公开(公告)日：2022-06-30

申请号：US17134333

申请日：2020-12-26

申请人： Intel Corporation

发明人： Richard Winterton ,  Mohammad Reza Haghighat ,  Asit Mallick ,  Alaa Alameldeen ,  Abhishek Basak ,  Jason W. Brandt ,  Michael Chynoweth ,  Carlos Rozas ,  Scott Constable ,  Martin Dixon ,  Matthew Fernandez ,  Fangfei Liu ,  Francis McKeen ,  Joseph Nuzman ,  Gilles Pokam ,  Thomas Unterluggauer ,  Xiang Zou

IPC分类号： G06F21/60 ,  H04L9/08 ,  H04L9/30

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.

公开(公告)号：US20220207148A1

公开(公告)日：2022-06-30

申请号：US17134345

申请日：2020-12-26

申请人： Intel Corporation

发明人： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC分类号： G06F21/57 ,  G06F9/38 ,  G06F21/54

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.

公开(公告)号：US20220207146A1

公开(公告)日：2022-06-30

申请号：US17134341

申请日：2020-12-26

申请人： Intel Corporation

发明人： Carlos Rozas ,  Fangfei Liu ,  Xiang Zou ,  Francis McKeen ,  Jason W. Brandt ,  Joseph Nuzman ,  Alaa Alameldeen ,  Abhishek Basak ,  Scott Constable ,  Thomas Unterluggauer ,  Asit Mallick ,  Matthew Fernandez

IPC分类号： G06F21/57 ,  G06F9/38 ,  G06F21/54

摘要： Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and load circuitry coupled to the decode circuitry. The decode circuitry is to decode a load hardening instruction to mitigate vulnerability to a speculative execution attack. The load circuitry is to be hardened in response to the load hardening instruction.

公开(公告)号：US10776190B2

公开(公告)日：2020-09-15

申请号：US16224579

申请日：2018-12-18

申请人： Intel Corporation

发明人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F12/00 ,  G06F9/38 ,  G06F12/109 ,  G06F21/60 ,  G06F12/14

摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US20200285578A1

公开(公告)日：2020-09-10

申请号：US16822939

申请日：2020-03-18

申请人： Intel Corporation

发明人： Ren Wang ,  Joseph Nuzman ,  Samantika S. Sury ,  Andrew J. Herdrich ,  Namakkal N. Venkatesan ,  Anil Vasudevan ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell

IPC分类号： G06F12/0831 ,  G06F12/084 ,  G06F12/0811

摘要： Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

公开(公告)号：US20190138451A1

公开(公告)日：2019-05-09

申请号：US16235276

申请日：2018-12-28

申请人： Intel Corporation

发明人： Hanna Alam ,  Joseph Nuzman

IPC分类号： G06F12/0862 ,  G06F12/0877

摘要： Disclosed embodiments relate to systems and methods structured to predict and prefetch a cache access based on a delta pattern. In one example, a processor is structured to extract a delta history corresponding to a delta pattern and a current page, generate a bucketed delta history based on the delta history corresponding to the current page, select a prediction entry based on the bucketed delta history, generate one or more prefetch candidates based on a confidence threshold, the confidence threshold structured to indicate one or more probable delta patterns, and filter the one or more prefetch candidates.

公开(公告)号：US10162694B2

公开(公告)日：2018-12-25

申请号：US14977354

申请日：2015-12-21

申请人： Intel Corporation

发明人： Tomer Stark ,  Ron Gabor ,  Joseph Nuzman ,  Raanan Sade ,  Bryant E. Bigbee

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F12/00 ,  G06F9/38

摘要： Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

公开(公告)号：US10157136B2

公开(公告)日：2018-12-18

申请号：US15087917

申请日：2016-03-31

申请人： Intel Corporation

发明人： Leeor Peled ,  Joseph Nuzman ,  Larisa Novakovsky

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0862 ,  G06F12/0897

摘要： A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a pipelined prefetcher, and a retirement unit to retire instructions. The prefetcher includes circuitry to receive a demand request for data at a first address within a first line in a memory and, in response, to provide the data at the first address to the execution unit for consumption, to prefetch a second line at a first offset distance from the first line into a mid-level cache, and to prefetch a third line at a second offset distance from the second line into a last-level cache. The prefetcher includes circuitry to prefetch, in response to another demand request, the third line into the mid-level cache, and a fourth line into the last-level cache. The prefetcher enforces minimum or maximum offset distances between prefetched data streams.