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公开(公告)号：US11093278B2
公开(公告)日：2021-08-17
申请号：US16605539
申请日：2017-06-30
Applicant: Intel Corporation
Inventor： Michael Chynoweth , Rajshree Chabukswar , Eliezer Weissmann , Jeremy Shrall
Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.
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Patent Agency Ranking
公开(公告)号：US11693588B2
公开(公告)日：2023-07-04
申请号：US15929272
申请日：2020-04-21
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Michael Chynoweth , Rajshree Chabukswar , Muhammad Taher
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0653 , G06F3/0673 , G06F11/3466
Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.
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公开(公告)号：US20220207154A1
公开(公告)日：2022-06-30
申请号：US17134333
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Richard Winterton , Mohammad Reza Haghighat , Asit Mallick , Alaa Alameldeen , Abhishek Basak , Jason W. Brandt , Michael Chynoweth , Carlos Rozas , Scott Constable , Martin Dixon , Matthew Fernandez , Fangfei Liu , Francis McKeen , Joseph Nuzman , Gilles Pokam , Thomas Unterluggauer , Xiang Zou
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.
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公开(公告)号：US12216932B2
公开(公告)日：2025-02-04
申请号：US18327474
申请日：2023-06-01
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Michael Chynoweth , Rajshree Chabukswar , Muhammad Taher
Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.
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公开(公告)号：US20220206819A1
公开(公告)日：2022-06-30
申请号：US17134335
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Gilles Pokam , Asit Mallick , Martin Dixon , Michael Chynoweth
Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability mitigation hardware and speculation vulnerability detection hardware. The speculation vulnerability mitigation hardware is to implement one or more of a plurality of speculation vulnerability mitigation mechanisms. The speculation vulnerability detection hardware to detect vulnerability to a speculative execution attack and to provide to software an indication of speculative execution attack vulnerability.
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公开(公告)号：US10649688B1
公开(公告)日：2020-05-12
申请号：US16177642
申请日：2018-11-01
Applicant: Intel Corporation
Inventor： Ahmad Yasin , Michael Chynoweth , Rajshree Chabukswar , Muhammad Taher
Abstract: A processor includes a memory subsystem having a first memory subunit that includes a status register and an execution engine unit coupled to the memory subsystem. The execution engine unit is to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit stores a piece of information, related to a status of the load operation, in the status register. Responsive to detection of retirement of the load operation, the first memory subunit is to store the piece of information from the status register into a particular field of a record of a memory buffer, wherein the particular field is associated with the first memory subunit.
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