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    Package substrate having photo-sensitive dielectric layer and method of fabricating the same
    1.
    发明授权
    Package substrate having photo-sensitive dielectric layer and method of fabricating the same 有权
    具有光敏介电层的封装基板及其制造方法

    公开(公告)号：US09485874B2

    公开(公告)日：2016-11-01

    申请号：US14010250

    申请日：2013-08-26

    Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corporation

    Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Dyi-Chung Hu ,  Chang-Hong Hsieh

    IPC: H05K1/11 ,  H05K3/40 ,  H01L23/14 ,  H01L23/498

    CPC classification number: H05K3/4038 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/115 ,  Y10T29/49165

    Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate may include an interposer having at least one conductive through via, a photo-sensitive dielectric layer formed on one side of the interposer, and at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through via. By means of a photo lithography process with high alignment accuracy, at least one via with an extremely small diameter can be formed on the photo-sensitive dielectric layer and align with the conductive through via. Therefore, the conductive through via can have its diameter reduced as required, without considering the alignment with the at least one via. Accordingly, the interconnection density of the conductive through via on the interposer is increased.

    Abstract translation: 提供封装基板和制造封装基板的方法。 封装衬底可以包括具有至少一个导电通孔，形成在插入器的一侧上的光敏电介质层和至少一个形成在光敏电介质层中的导电通孔并且与导电通孔 通过。 通过具有高对准精度的光刻工艺，可以在感光介电层上形成至少一个具有极小直径的通孔，并与导电通孔对齐。 因此，导电通孔可以根据需要减小其直径，而不考虑与至少一个通孔的对准。 因此，插入件上的导电贯通孔的互连密度增加。

    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE
    4.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME AND CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210082810A1

    公开(公告)日：2021-03-18

    申请号：US17095744

    申请日：2020-11-12

    Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

    Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Tao-Chih Chang ,  Yu-Min Lin ,  Sheng-Tsai Wu

    IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/04

    Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210066189A1

    公开(公告)日：2021-03-04

    申请号：US17095742

    申请日：2020-11-12

    Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

    Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Dyi-Chung Hu ,  Chang-Hong HSIEH

    IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/04

    Abstract: A package substrate includes a substrate, an interposer and an insulating protective layer. The substrate has a first surface and a second surface opposing to the first surface. The first surface includes a plurality of first conductive pads. The interposer is disposed on the first surface of the substrate such that the first conductive pads are partially covered by the interposer. The interposer includes a plurality of penetrating conductive vias electrically connected to the substrate. The insulating protective layer is disposed on the first surface of the substrate and surrounding the interposer. The insulating protective layer includes at least one penetrating conductive column, wherein a first width of the respective penetrating conductive column is greater than a second width of each of the penetrating conductive vias of the interposer.

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