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    Layout to reduce current crowding at endpoints
    1.
    发明授权
    Layout to reduce current crowding at endpoints 有权

    公开(公告)号：US11777018B2

    公开(公告)日：2023-10-03

    申请号：US17523513

    申请日：2021-11-10

    Applicant: IDEAL POWER INC.

    Inventor： Richard A. Blanchard ,  Alireza Mojab

    IPC: H01L29/06 ,  H01L29/732

    CPC classification number: H01L29/732

    Abstract: Layout to reduce current crowding at endpoints. At least one example is a semiconductor device comprising: an emitter region defining an inner boundary in the shape of an obround with parallel sides, and the obround having hemispherical ends each having a radius; a base region having a first end, a second end opposite the first end, and base length, the base region disposed within the obround with the base length parallel to and centered between the parallel sides, the first end spaced apart from the first hemispherical end by a first gap greater than the radius, and the second end spaced apart from the second hemispherical ends by a second gap greater than the radius.

    Systems and methods for bidirectional device fabrication
    2.
    发明授权
    Systems and methods for bidirectional device fabrication 有权

    公开(公告)号：US11637016B2

    公开(公告)日：2023-04-25

    申请号：US16150409

    申请日：2018-10-03

    Applicant: Ideal Power Inc.

    Inventor： Richard A. Blanchard ,  William C. Alexander

    IPC: H01L21/225 ,  H01L21/324 ,  H01L21/768 ,  H01L21/683

    Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

    Circuits, methods, and systems with optimized operation of double-base bipolar junction transistors
    10.
    发明授权
    Circuits, methods, and systems with optimized operation of double-base bipolar junction transistors 有权
    具有双基极双极结晶体管优化工作的电路，方法和系统

    公开(公告)号：US09444449B2

    公开(公告)日：2016-09-13

    申请号：US14935344

    申请日：2015-11-06

    Applicant: Ideal Power Inc.

    Inventor： William C. Alexander ,  Richard A. Blanchard

    IPC: H03K17/0412 ,  H03K17/60 ,  H01L29/747 ,  H01L29/74 ,  H01L29/872

    CPC classification number: H03K17/66 ,  H01L27/0694 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/7302 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7412 ,  H01L29/7416 ,  H01L29/747 ,  H01L29/872 ,  H02M1/08 ,  H02M7/219 ,  H02M2007/2195 ,  H03K17/60 ,  H03K17/602 ,  H03K17/687 ,  H03K2217/0054

    Abstract: The present application teaches, inter alia, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). Exemplary base drive circuits provide high-impedance drive to the base contact region on the side of the device instantaneously operating as the collector. (The B-TRAN is controlled by applied voltage rather than applied current.) Current signals operate preferred implementations of drive circuits to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with low voltage drop (the “transistor-ON” state). In some preferred embodiments, self-synchronizing rectifier circuits provide adjustable low voltage for gate drive circuits. In some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while base current at that terminal is monitored, so no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.

    Abstract translation: 本申请尤其教导了用于操作B-TRAN（双基极双极结型晶体管）的方法和电路。 示例性的基本驱动电路向作为集电器瞬时操作的装置一侧的基极接触区域提供高阻抗驱动。 （B-TRAN由施加的电压而不是施加电流控制。）电流信号操作驱动电路的优选实施方式，以提供二极管模式导通和预关断操作，以及具有低电压降的硬导通状态（ “晶体管导通”状态）。 在一些优选实施例中，自同步整流电路为栅极驱动电路提供可调节的低电压。 在一些优选实施例中，用于驱动c基极区域（集电极侧）的基极驱动电压随着该端子处的基极电流被监测而变化，因此不再施加所需的基极电流。 这解决了在B-TRAN中优化基础驱动的困难挑战。

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