Fault Information Processing Method and Apparatus

    公开(公告)号:US20240283695A1

    公开(公告)日:2024-08-22

    申请号:US18649140

    申请日:2024-04-29

    CPC classification number: H04L41/06

    Abstract: A fault information processing method implemented by a first interface with a physical layer (PHY) chip and a media access control layer (MAC) chip, includes, after receiving first fault information sent by a second interface communicating with the first interface, sending by the PHY chip second fault information to the MAC chip, where the first fault information indicates that the second interface detects a fault, and the second fault information indicates that the fault is from the second interface. Because the PHY chip has received the first fault information, a link between the PHY chip and the second interface is normal. Because the MAC chip can normally receive the second fault information, it indicates that communication between the PHY chip and the MAC chip is normal. The fault information processing method is used to determine the fault from the second interface.

    Systems and methods for compensating polarization dependent loss (PDL) in dual polarized communication network

    公开(公告)号:US11770276B1

    公开(公告)日:2023-09-26

    申请号:US17962060

    申请日:2022-10-07

    CPC classification number: H04L25/03057 H04B7/10

    Abstract: The disclosed systems and methods for compensating the polarization dependent loss (PDL) in communication networks comprising: i) filtering, by a first feed-forward filter, a current set of symbols in an equalized X-Pol signal; ii) filtering, by a second feed-forward filter, a current set of symbols in an equalized Y-Pol signal; iii) filtering, by a first feed-backward filter, a previously decided set of symbols associated with the equalized X-Pol signal; iv) filtering, by a second feed-backward filter a previously decided set of symbols associated with the equalized Y-Pol signal; v) adding, by a first adder, the outputs from the first feed-forward filter and the second feed-forward filter; and vi) subtracting, by the first adder, the outputs from the first feed-backward filter and the second feed-backward filter from the addition of outputs from the first feed-forward filter and the second feed-forward filter to determine the symbols in the equalized X-Pol signal.

    Cabinet and heat dissipation system

    公开(公告)号:US10278309B2

    公开(公告)日:2019-04-30

    申请号:US15785159

    申请日:2017-10-16

    Abstract: The present disclosure provides a cabinet and a heat dissipation system. The cabinet includes: an operating compartment, disposed on one side of a heat dissipation substrate, where the operating compartment is configured to accommodate a server; and a heat dissipation compartment, disposed on the other side of the heat dissipation substrate. Both the heat dissipation compartment and the operating compartment share the heat dissipation substrate as a compartment wall. The operating compartment is separated from the heat dissipation compartment by using the heat dissipation substrate. The heat dissipation compartment accommodates multiple heat dissipation fins, and the multiple heat dissipation fins are connected to the heat dissipation substrate. An air intake vent is disposed in a first compartment wall of the heat dissipation compartment, and an air exhaust vent is disposed in a second compartment wall of the heat dissipation compartment disclosure.

    Data frame sending method and apparatus

    公开(公告)号:US09882822B2

    公开(公告)日:2018-01-30

    申请号:US14984474

    申请日:2015-12-30

    Abstract: A data frame sending method and apparatus for effectively improving sending efficiency by, acquiring a basic speed set, determining a current sending speed which is the maximum speed in a candidate speed set, and the candidate speed set is the set of elements from the basic speed set and whose packet sending success rate is greater than a threshold, acquiring an aggregation length value according to the current sending speed, where the aggregation length value is the maximum length of a frame that can be sent at the current sending speed, determining multiple medium access control (MAC) protocol data units (MPDUs) from to-be-sent MPDUs according to the aggregation length value, and aggregating the multiple MPDUs to obtain an aggregate MAC protocol data unit (A-MPDU), where a length of the A-MPDU is less than or equal to the aggregation length value, and sending the A-MPDU at the current sending speed.

    Data Frame Sending Method and Apparatus
    8.
    发明申请
    Data Frame Sending Method and Apparatus 有权
    数据帧发送方法和装置

    公开(公告)号:US20160191403A1

    公开(公告)日:2016-06-30

    申请号:US14984474

    申请日:2015-12-30

    Abstract: A data frame sending method and apparatus for effectively improving sending efficiency by, acquiring a basic speed set, determining a current sending speed which is the maximum speed in a candidate speed set, and the candidate speed set is the set of elements from the basic speed set and whose packet sending success rate is greater than a threshold, acquiring an aggregation length value according to the current sending speed, where the aggregation length value is the maximum length of a frame that can be sent at the current sending speed, determining multiple medium access control (MAC) protocol data units (MPDUs) from to-be-sent MPDUs according to the aggregation length value, and aggregating the multiple MPDUs to obtain an aggregate MAC protocol data unit (A-MPDU), where a length of the A-MPDU is less than or equal to the aggregation length value, and sending the A-MPDU at the current sending speed.

    Abstract translation: 一种用于通过获取基本速度集,确定作为候选速度集合中的最大速度的当前发送速度和候选速度集合来有效地提高发送效率的数据帧发送方法和装置是从基本速度 并且其分组发送成功率大于阈值,根据当前发送速度获取聚合长度值,其中聚合长度值是可以当前发送速度发送的帧的最大长度,确定多个媒体 根据聚合长度值从待发送MPDU的接入控制(MAC)协议数据单元(MPDU),并聚合多个MPDU以获得聚合MAC协议数据单元(A-MPDU),其中A的长度 -MPDU小于或等于聚合长度值,并以当前发送速度发送A-MPDU。

    Multi-Instruction Engine-Based Instruction Processing Method and Processor

    公开(公告)号:US20230267002A1

    公开(公告)日:2023-08-24

    申请号:US18309177

    申请日:2023-04-28

    Inventor: Jin Wang

    CPC classification number: G06F9/4881 G06F9/30047

    Abstract: A processor includes a program block dispatcher, an instruction cache group, and an instruction engine group. A plurality of instruction caches in the instruction cache group are in a one-to-one correspondence with a plurality of instruction engines in the instruction engine group. In a method, the program block dispatcher determines, based on an instruction processing request for processing a first instruction set, a first instruction engine for processing the first instruction set; and determines, based on the one-to-one correspondence between the instruction engines and the instruction caches, a first instruction cache configured to cache the first instruction set. The program block dispatcher sends a program counter in the instruction processing request to the first instruction cache. The first instruction engine obtains the first instruction set from the first instruction cache, to execute an instruction in the first instruction set.

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