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公开(公告)号：US11838181B2
公开(公告)日：2023-12-05
申请号：US17831158
申请日：2022-06-02
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Hongliang Sun , Dawei Fan
IPC: G06F15/177 , H04L41/084 , H04L41/0893
CPC classification number: H04L41/084 , H04L41/0893
Abstract: A first network device determines configuration information of a target flexible Ethernet (FlexE) group to be adjusted, and adjusts the target FlexE group synchronously with a second network device based on the configuration information of the target FlexE group. The second network device communicates with the first network device through a physical layer link in the target FlexE group. The configuration information of the target FlexE group includes a backup FlexE group number and a backup FlexE map of the target FlexE group, and the backup FlexE map includes information about the physical layer link in the target FlexE group. The first network device and the second network device perform synchronous adjustment.
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公开(公告)号：US11843452B2
公开(公告)日：2023-12-12
申请号：US18146634
申请日：2022-12-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
IPC: H04J3/06
CPC classification number: H04J3/0661
Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
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公开(公告)号：US11108485B2
公开(公告)日：2021-08-31
申请号：US16860688
申请日：2020-04-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
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4.发明申请公开(公告)号：US20240421962A1
公开(公告)日：2024-12-19
申请号：US18820805
申请日：2024-08-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Xinyuan Wang , Hao Ren
Abstract: In a data processing method, a first device obtains at least one service flow, where any service flow in the at least one service flow includes a plurality of code blocks, and the code block includes a data unit and a type, or the code block includes a type, a type indication, and code block content; and the first device maps the plurality of code blocks to at least one PHY link based on a coding scheme of the code blocks, where the at least one PHY link is used to transmit the plurality of code blocks.
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公开(公告)号：US20240356845A1
公开(公告)日：2024-10-24
申请号：US18749849
申请日：2024-06-21
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Tongtong Wang , Xinyuan Wang
Abstract: A method for generating an Ethernet frame includes generating the Ethernet frame including a protection field, where a protection range of the protection field includes a destination MAC address field in the Ethernet frame. A method for processing an Ethernet frame includes receiving a plurality of bytes in the Ethernet frame, where the plurality of bytes include information about the destination MAC address field and information about the protection field; and checking information within the protection range of the protection field based on the information about the protection field.
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Patent Agency Ranking
公开(公告)号：US20240283695A1
公开(公告)日：2024-08-22
申请号：US18649140
申请日：2024-04-29
Applicant: Huawei Technologies Co., Ltd.
IPC: H04L41/06
CPC classification number: H04L41/06
Abstract: A fault information processing method implemented by a first interface with a physical layer (PHY) chip and a media access control layer (MAC) chip, includes, after receiving first fault information sent by a second interface communicating with the first interface, sending by the PHY chip second fault information to the MAC chip, where the first fault information indicates that the second interface detects a fault, and the second fault information indicates that the fault is from the second interface. Because the PHY chip has received the first fault information, a link between the PHY chip and the second interface is normal. Because the MAC chip can normally receive the second fault information, it indicates that communication between the PHY chip and the MAC chip is normal. The fault information processing method is used to determine the fault from the second interface.
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公开(公告)号：US20240223684A1
公开(公告)日：2024-07-04
申请号：US18600191
申请日：2024-03-08
Applicant: Huawei Technologies Co., Ltd.
CPC classification number: H04L69/24 , H04L1/0072 , H04L1/0076
Abstract: An interface obtains basic page information from another interface. The basic page information includes N bits, the N bits include an FEC function indicator bit sequence including an FEC ability indicator bit and an FEC requested indicator bit. The interface determines, based on values of a plurality of bits in the N bits, an operation mode supported by the another interface. The FEC function indicator bit sequence includes a first FEC function indicator bit corresponding to m FEC abilities; or the FEC function indicator bit sequence includes a first FEC ability indicator bit corresponding to n FEC abilities, where both m and n are greater than or equal to 1. Because one FEC function indicator bit indicates more FEC abilities, N bits in a basic page can carry more information, so that a process of increasing auto-negotiation pages is slowed down, thereby avoiding impact on auto-negotiation efficiency.
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公开(公告)号：US20220303035A1
公开(公告)日：2022-09-22
申请号：US17833862
申请日：2022-06-06
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
IPC: H04J3/06 , H03M9/00 , H04J3/16 , H04L69/323
Abstract: This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.
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公开(公告)号：US20210376943A1
公开(公告)日：2021-12-02
申请号：US17403131
申请日：2021-08-16
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
IPC: H04J3/06
Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
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公开(公告)号：US20200259578A1
公开(公告)日：2020-08-13
申请号：US16860688
申请日：2020-04-28
Applicant: Huawei Technologies Co., Ltd.
Inventor： Xiang He , Yunlei Qi , Jingfeng Chen , Tao Lin , Junmin Song , Xinyuan Wang
IPC: H04J3/06
Abstract: A clock synchronization method includes receiving, by a receiving apparatus, a plurality of data blocks using a plurality of physical layer modules (PHYs), where the plurality of data blocks include a plurality of head data blocks, performing, by the receiving apparatus, timestamp sampling on the plurality of data blocks to generate a plurality of receipt timestamps, aligning, by the receiving apparatus, the plurality of receipt timestamps using a first receipt timestamp as a reference, generating, by the receiving apparatus, a clock synchronization packet based on the plurality of data blocks, and writing, by the receiving apparatus, a value of a second receipt timestamp into the clock synchronization packet, where the second receipt timestamp is a receipt timestamp that is of a second data block and that is determined based on the plurality of aligned receipt timestamps.
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