公开(公告)号：US08880780B2

公开(公告)日：2014-11-04

申请号：US13215789

申请日：2011-08-23

申请人： Hong Beom Pyeon ,  Kin-Ki Kim ,  HakJune Oh

发明人： Hong Beom Pyeon ,  Kin-Ki Kim ,  HakJune Oh

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F13/42

CPC分类号： G06F13/4243 ,  G06F13/4247

摘要： An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.

摘要翻译： 提供了一种使用存储器件的页缓冲器作为数据的临时缓存的装置和方法。 存储器控制器将数据写入页缓冲器，并且随后读出数据而不将数据编程到存储器件的存储单元中。 这允许存储器控制器使用页面缓冲器作为临时缓存，使得数据不必占用存储器控制器的本地数据存储元件内的空间。 因此，存储器控制器可以将其自己的存储元件中的空间用于其他操作。

公开(公告)号：US08812768B2

公开(公告)日：2014-08-19

申请号：US12033577

申请日：2008-02-19

申请人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Steven Przybylski ,  Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G06F12/00

CPC分类号： G06F3/0629 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C7/1042 ,  G11C7/20 ,  G11C8/06 ,  G11C8/10 ,  Y02D10/14 ,  Y02D10/151

摘要： A system having serially connected memory devices in a ring topology organization to realize high speed performance. The memory devices have dynamically configurable data widths such that the system can operate with up to a maximum common number of active data pads to maximize performance, or to operate with a single active data pad to minimize power consumption. Therefore the system can include a mix of memory devices having different data widths. The memory devices are dynamically configurable through the issuance of a single command propagated serially through all the memory devices from the memory controller in a broadcast operation. Robust operation of the system is ensured by implementing a data output inhibit algorithm, which prevents valid data from being provided to the memory controller when read output control signal is received out of its proper sequence.

摘要翻译： 一种在环形拓扑组织中具有串联连接的存储器件以实现高速性能的系统。 存储器件具有动态可配置的数据宽度，使得系统可以以高达最大公共数量的有源数据焊盘操作以最大化性能，或者使用单个有源数据焊盘操作以最小化功耗。 因此，系统可以包括具有不同数据宽度的存储器件的混合。 通过在广播操作中通过从存储器控制器的所有存储器装置串行传播的单个命令的发布来动态地配置存储器件。 通过实施数据输出禁止算法来确保系统的稳健运行，当从其正确的序列中接收到读取输出控制信号时，该算法防止有效数据被提供给存储器控制器。

公开(公告)号：US08363444B2

公开(公告)日：2013-01-29

申请号：US13365895

申请日：2012-02-03

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G11C7/02

CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

摘要： A bridge device architecture for connecting discrete memory devices. The bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device includes a local control interface for connecting to the at least one discrete memory device, a local input/output interface for connecting to the at least one discrete memory device, and a global input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

摘要翻译： 用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括用于连接至少一个分立存储器件的本地控制接口，用于连接至少一个分立存储器件的本地输入/输出接口以及全局输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

公开(公告)号：US08060691B2

公开(公告)日：2011-11-15

申请号：US13022166

申请日：2011-02-07

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4243 ,  G06F13/4247

摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

摘要翻译： 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US20110258366A1

公开(公告)日：2011-10-20

申请号：US13023838

申请日：2011-02-09

申请人： Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Roland Schuetz ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G06F12/00

CPC分类号： G11C7/1063 ,  G11C16/06

摘要： Status indication in a system having a plurality of memory devices is disclosed. A memory device in the system includes a plurality of data pins for connection to a data bus. The memory device also includes a status pin for connection to a status line that is independent from the data bus. The memory device also includes first circuitry for generating, upon completion of a memory operation having a first duration, a strobe pulse of a second duration much shorter than the first duration. The strobe pulse provides an indication of the completion of the memory operation. The memory device also includes second circuitry for outputting the strobe pulse onto the status line via the status pin.

摘要翻译： 公开了具有多个存储器件的系统中的状态指示。 系统中的存储器件包括用于连接到数据总线的多个数据引脚。 存储器件还包括用于连接到独立于数据总线的状态线的状态引脚。 存储器件还包括第一电路，用于在完成具有第一持续时间的存储器操作时产生比第一持续时间短得多的第二持续时间的选通脉冲。 选通脉冲提供存储器操作完成的指示。 存储器件还包括用于经由状态引脚将选通脉冲输出到状态线上的第二电路。

公开(公告)号：US07515471B2

公开(公告)日：2009-04-07

申请号：US11583354

申请日：2006-10-19

申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US20080181214A1

公开(公告)日：2008-07-31

申请号：US11692452

申请日：2007-03-28

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

IPC分类号： H04L12/56

CPC分类号： G06F13/4243

摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the several interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.

摘要翻译： 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。 根据设备类型匹配确定，DT与所生成或接收的ID组合。 组合的DT和ID作为传送到下一个设备的分组。 在多个互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 参考提供给互连设备的设备类型，依次生成ID。 将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

公开(公告)号：US20080080492A1

公开(公告)日：2008-04-03

申请号：US11529293

申请日：2006-09-29

申请人： Hong Beom Pyeon ,  HakJune Oh

发明人： Hong Beom Pyeon ,  HakJune Oh

IPC分类号： H04J1/16 ,  H04L12/56

CPC分类号： G06F1/12 ,  G06F1/04 ,  G11C5/00 ,  G11C5/066 ,  G11C7/20

摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

摘要翻译： 各种存储器件（例如，DRAM，闪存）串联连接。 存储器件需要其标识符（ID）。 每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。 命令数据和先前生成的ID数据被同步地注册。 注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。 计算是一个加法或减法。 通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。 响应于解释的ID和时钟来控制时钟延迟。 根据受控时钟延迟，以分组为基础提供新的ID。 在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

公开(公告)号：US09183892B2

公开(公告)日：2015-11-10

申请号：US13765059

申请日：2013-02-12

申请人： HakJune Oh ,  Jin-Ki Kim ,  Hong Beom Pyeon

发明人： HakJune Oh ,  Jin-Ki Kim ,  Hong Beom Pyeon

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  G11C5/06 ,  G11C5/02 ,  G11C5/04 ,  H01L25/065

CPC分类号： G11C5/06 ,  G11C5/02 ,  G11C5/04 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/00015

摘要： A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through the memory devices.

摘要翻译： 第一存储器件和第二存储器件具有相同的输入/输出布局配置。 为了形成堆叠，第二存储器件被固定到第一存储器件。 为了便于连接，第二存储器设备相对于堆叠中的第一存储器设备旋转偏移，以使第一存储器件的输出与第二存储器件的相应输入相对准。 第二存储器件相对于第一存储器件的旋转偏移将第一存储器件的一个或多个输出与第二存储器件的一个或多个相应的输入对准。 基于输出之间的链路和堆叠中的一个存储设备到另一存储设备的输入，存储器设备堆叠可以包括便于通过存储器设备的一个或多个串联连接配置的路径。

公开(公告)号：US08700818B2

公开(公告)日：2014-04-15

申请号：US11529293

申请日：2006-09-29

申请人： Hong Beom Pyeon ,  HakJune Oh

发明人： Hong Beom Pyeon ,  HakJune Oh

IPC分类号： G06F3/00 ,  G06F1/12

CPC分类号： G06F1/12 ,  G06F1/04 ,  G11C5/00 ,  G11C5/066 ,  G11C7/20

摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.

摘要翻译： 各种存储器件（例如，DRAM，闪存）串联连接。 存储器件需要它们的标识符（ID）。 每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。 命令数据和先前生成的ID数据被同步地注册。 注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。 计算是一个加法或减法。 通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。 响应于解释的ID和时钟来控制时钟延迟。 根据受控时钟延迟，以分组为基础提供新的ID。 在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。