公开(公告)号：US20100097105A1

公开(公告)日：2010-04-22

申请号：US12445390

申请日：2007-11-20

Applicant: Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H03B1/00 ,  H01L29/20 ,  H01L29/24 ,  H01L29/772 ,  H03K17/56

CPC classification number: H01L29/7787 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/739 ,  H01L29/8124

Abstract: A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

Abstract translation: 半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。 在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

公开(公告)号：US06933542B2

公开(公告)日：2005-08-23

申请号：US10768040

申请日：2004-02-02

Applicant: Hidetoshi Ishida ,  Tsuyoshi Tanaka

Inventor： Hidetoshi Ishida ,  Tsuyoshi Tanaka

IPC: H01L21/335 ,  H01L27/06 ,  H01L29/778 ,  H01L31/109 ,  H01L29/739

CPC classification number: H01L29/66462 ,  H01L27/0605 ,  H01L29/7783

Abstract: A channel layer made of undoped InGaAs, a carrier supply layer made of n-type AlGaAs, a Schottky layer made of disordered InGaP without a natural superlattice structure, and a cap layer made of GaAs are successively stacked on a compound semiconductor substrate. A gate electrode is formed on a part of the Schottky layer exposed at the opening of the cap layer. Source and dram electrodes are formed on the cap layer. The thickness of the Schottky layer is set at about 8 nm or less. As a result, the reverse breakdown voltage of the gate electrode becomes larger than that in the case of a Schottky layer made of AlGaAs.

Abstract translation: 由n型AlGaAs构成的载流子供给层，由天然超晶格结构的无序InGaP构成的肖特基以及由GaAs构成的盖层构成的沟道层依次层叠在化合物半导体基板上。 栅极电极形成在暴露在盖层开口处的肖特基层的一部分上。 源极和引脚电极形成在盖层上。 肖特基层的厚度设定为约8nm以下。 结果，栅电极的反向击穿电压变得大于由AlGaAs制成的肖特基层的情况。

公开(公告)号：US06365513B1

公开(公告)日：2002-04-02

申请号：US09162232

申请日：1998-09-29

Applicant: Hidetoshi Furukawa ,  Atsushi Noma ,  Tsuyoshi Tanaka ,  Hidetoshi Ishida ,  Daisuke Ueda

Inventor： Hidetoshi Furukawa ,  Atsushi Noma ,  Tsuyoshi Tanaka ,  Hidetoshi Ishida ,  Daisuke Ueda

IPC: H01L2166

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

Abstract translation: 在衬底中形成具有底部的通孔，然后在通孔的至少一个侧壁上形成导体层。 此后，通过去除衬底的与形成通孔的衬底的另一部分相对的部分使得导体层暴露而使衬底变薄。

公开(公告)号：US07859087B2

公开(公告)日：2010-12-28

申请号：US12637240

申请日：2009-12-14

Applicant: Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L23/58

CPC classification number: H01L29/7787 ,  H01L23/367 ,  H01L23/3677 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

公开(公告)号：US20100090250A1

公开(公告)日：2010-04-15

申请号：US12637240

申请日：2009-12-14

Applicant: Tomohiro MURATA ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Tomohiro MURATA ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L29/205 ,  H01L29/772 ,  H01L29/06

CPC classification number: H01L29/7787 ,  H01L23/367 ,  H01L23/3677 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

Abstract translation: 半导体器件包括：半导体层; 形成在与半导体层接触的半导体层上的至少一个电极; 以及覆盖半导体层和电极的顶表面的至少一部分的钝化膜，以保护半导体层并由多个子膜形成。 钝化膜包括由氮化铝制成的第一子膜。

公开(公告)号：US20060124962A1

公开(公告)日：2006-06-15

申请号：US11297386

申请日：2005-12-09

Applicant: Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

Inventor： Tetsuzo Ueda ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

IPC: H01L31/0328

CPC classification number: H01L21/28581 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A field effect transistor includes a first semiconductor layer made of a multilayer of a plurality of semiconductor films and a second semiconductor layer formed on the first semiconductor layer. A source electrode and a drain electrode are formed on the second semiconductor layer to be spaced from each other. An opening having an insulating film on its inner wall is formed in a portion of the second semiconductor layer sandwiched between the source electrode and the drain electrode so as to expose the first semiconductor layer therein. A gate electrode is formed in the opening to be in contact with the insulating film and the first semiconductor layer on the bottom of the opening.

Abstract translation: 场效应晶体管包括由多个半导体膜的多层构成的第一半导体层和形成在第一半导体层上的第二半导体层。 源电极和漏电极形成在第二半导体层上以彼此间隔开。 在夹在源电极和漏极之间的第二半导体层的一部分中形成有在其内壁上具有绝缘膜的开口，以便在其中露出第一半导体层。 在开口部形成有与绝缘膜和开口底部的第一半导体层接触的栅电极。

公开(公告)号：US20050051793A1

公开(公告)日：2005-03-10

申请号：US10912567

申请日：2004-08-06

Applicant: Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L29/20 ,  H01L29/423 ,  H01L29/778 ,  H01L29/417

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/7787 ,  Y10S257/918

Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which consists of silicon carbide or sapphire, and consisting of a general formula InxGa1-xN, where 0≦x≦1; a second compound layer formed on the first compound layer, and consisting of a general formula IyAlzGa1-y-zN, where 0≦y≦1 and 0

Abstract translation: 开关半导体器件包括形成在由碳化硅或蓝宝石构成的单晶衬底上并由通式In x Ga 1-x N构成的第一化合物层，其中0 <= x <= 1; 由第一化合物层形成并由通式IyAlzGa1-y-zN组成的第二化合物层，其中0 <= y <= 1且0

公开(公告)号：US07683399B2

公开(公告)日：2010-03-23

申请号：US11758304

申请日：2007-06-05

Applicant: Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L31/0328

CPC classification number: H01L29/7787 ,  H01L29/045 ,  H01L29/0891 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/452

Abstract: There is provided a normally-off type transistor made of a nitride semiconductor. The transistor includes; an undoped GaN layer which forms a channel region; an undoped Al0.2Ga0.8N layer which is formed on the undoped GaN layer and has a band gap larger than that of the undoped GaN layer; a p-type Al0.2Ga0.8N control layer which is formed on the undoped Al0.2Ga0.8N layer, has a p-type conductivity and forms a control region; an Ni gate electrode which contacts with the p-type Al0.2Ga0.8N control layer; a Ti/Al source electrode and a Ti/Al drain electrode which are formed beside the p-type Al0.2Ga0.8N control layer; and an Ni ohmic electrode which is connected to the undoped GaN layer and serves as a hole absorbing electrode. With this transistor, it is possible to achieve a large-current operation and a high switching speed.

Abstract translation: 提供了由氮化物半导体制成的常关型晶体管。 晶体管包括： 形成沟道区的未掺杂GaN层; 未掺杂的Al0.2Ga0.8N层，其形成在未掺杂的GaN层上，并且具有比未掺杂的GaN层的带隙大的带隙; 形成在未掺杂的Al0.2Ga0.8N层上的p型Al0.2Ga0.8N控制层具有p型导电性并形成控制区; 与p型Al0.2Ga0.8N控制层接触的Ni栅电极; 形成在p型Al0.2Ga0.8N控制层旁边的Ti / Al源电极和Ti / Al漏电极; 以及连接到未掺杂的GaN层并用作空穴吸收电极的Ni欧姆电极。 利用该晶体管，可以实现大电流动作和高切换速度。

公开(公告)号：US07439621B1

公开(公告)日：2008-10-21

申请号：US09707844

申请日：2000-11-08

Applicant: Hidetoshi Ishida ,  Kazuo Miyatsuji ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

Inventor： Hidetoshi Ishida ,  Kazuo Miyatsuji ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC: H01L23/34 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L27/0207 ,  H01L27/088 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The RF device of the present invention includes: a semiconductor substrate; and first and second semiconductor components provided on the substrate. Each of the components includes source electrodes, a gate electrode and a drain electrode. And multiple through holes, which pass through the substrate in the thickness direction, are opened in a region of the substrate between the two components. To enhance the effect of suppressing electrical interference between the components, a gap between two adjacent ones of the through holes is preferably smaller than the thickness of the substrate.

Abstract translation: 本发明的RF器件包括：半导体衬底; 以及设置在基板上的第一和第二半导体部件。 每个组件包括源电极，栅电极和漏电极。 并且在两个部件之间的基板的区域中打开穿过基板的厚度方向上的多个通孔。 为了增强抑制部件之间的电气干扰的效果，两个相邻的通孔之间的间隙优选小于基板的厚度。

公开(公告)号：US07332754B2

公开(公告)日：2008-02-19

申请号：US11022814

申请日：2004-12-28

Applicant: Takashi Uno ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

Inventor： Takashi Uno ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Tsuyoshi Tanaka

IPC: H01L29/80

CPC classification number: H01L27/1203 ,  H01L29/8126

Abstract: In the semiconductor switch of the present invention, the gate electrode, source electrode and drain electrode are formed such that the distance between the gate and the drain of an MESFET, assuming a shunt FET, is longer than the distance between the gate and the drain of an MESFET, assuming a through FET, so that the gate breakdown voltage of the MESFET, assuming a shunt FET, is increased without changing the gate breakdown voltage of the MESFET, assuming a through FET.

Abstract translation: 在本发明的半导体开关中，栅电极，源电极和漏极形成为使得MESFET的栅极和漏极之间的距离（假设分流FET）比栅极和漏极之间的距离长 假定通过FET，MESFET的假定为通过FET的MESFET的栅极击穿电压在不改变MESFET的栅极击穿电压的情况下增加，并且假定为通过FET，所以增加了MESFET的栅极击穿电压。