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    METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME
    2.
    发明申请
    METHOD FOR REDUCING WETTABILITY OF INTERCONNECT MATERIAL AT CORNER INTERFACE AND DEVICE INCORPORATING SAME 有权
    用于降低角接触面上的互连材料的湿度的方法和包含其的装置

    公开(公告)号：US20140210088A1

    公开(公告)日：2014-07-31

    申请号：US14227807

    申请日：2014-03-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xunyuan Zhang ,  Hoon Kim ,  Vivian W. Ryan

    IPC: H01L23/532

    CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy.

    Abstract translation: 半导体器件包括限定在电介质层中的凹部，凹部具有延伸到凹部的上角部的上侧壁部分和在上侧壁部分下方的下侧壁部分。 互连结构定位在凹槽中。 互连结构包括连续的衬垫层，其具有分别位于上下侧壁部分的横向相邻的上层和下层部分。 上层部分包括第一过渡金属和第二过渡金属的合金，下层部分包括第二过渡金属，但不包括第一过渡金属。 互连结构还包括基本上填充凹部的填充材料，其中第二过渡金属对于填充材料具有比合金更高的润湿性。

    Multi-layer barrier layer stacks for interconnect structures
    3.
    发明授权
    Multi-layer barrier layer stacks for interconnect structures 有权
    用于互连结构的多层势垒层堆叠

    公开(公告)号：US09076792B2

    公开(公告)日：2015-07-07

    申请号：US14287533

    申请日：2014-05-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC: H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L21/02 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768

    CPC classification number: H01L23/53209 ,  H01L21/02697 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess.

    Abstract translation: 半导体器件包括限定在介电层中的凹部和限定在凹部中的互连结构。 所述互连结构包括衬在所述凹部中的第一阻挡层，所述第一阻挡层包括钽合金和除了钽之外的第一过渡金属，其中所述第一阻挡层和所述介电层之间的第一界面具有第一应力水平。 第二阻挡层位于第一阻挡层上，第二阻挡层包括钽和氮化钽中的至少一个，其中第二阻挡层和第一阻挡层之间的第二界面具有小于第二阻挡层的第二应力水平 第一压力水平。 互连结构还包括基本上填充凹部的填充材料。

    METHODS OF FORMING NON-CONTINUOUS CONDUCTIVE LAYERS FOR CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT
    5.
    发明申请
    METHODS OF FORMING NON-CONTINUOUS CONDUCTIVE LAYERS FOR CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT 有权
    在集成电路产品上形成导电结构的非连续导电层的方法

    公开(公告)号：US20140246775A1

    公开(公告)日：2014-09-04

    申请号：US13781921

    申请日：2013-03-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Vivian W. Ryan ,  Xunyuan Zhang

    IPC: H01L21/768 ,  H01L23/498

    CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76868 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.

    Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料层上形成由多个间隔开的导电结构构成的非连续层，其中部分 未被多个间隔开的导电结构覆盖的绝缘材料层保持暴露，在非连续层上形成至少一个阻挡层，其中阻挡层接触间隔开的导电结构和该层的暴露部分 绝缘材料，在阻挡层上形成至少一个衬垫层，以及在衬里层上方的沟槽/通孔中形成导电结构。

    Subtractive metal multi-layer barrier layer for interconnect structure
    7.
    发明授权
    Subtractive metal multi-layer barrier layer for interconnect structure 有权
    用于互连结构的减金属多层势垒层

    公开(公告)号：US08623758B1

    公开(公告)日：2014-01-07

    申请号：US13657182

    申请日：2012-10-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC: H01L21/4763

    CPC classification number: H01L23/53238 ,  H01L21/76852 ,  H01L21/76858 ,  H01L2221/1078 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method includes forming an adhesion barrier layer over a dielectric layer formed on a substrate. A first stress level is present across a first interface between the adhesion barrier layer and the dielectric layer. A stress-reducing barrier layer is formed over the adhesion barrier layer. The stress-reducing barrier layer reduces the first stress level to provide a second stress level, less than the first stress level, across a second interface between the adhesion barrier layer, the stress-reducing barrier layer, and the dielectric layer. A metal layer is formed over the stress-reducing barrier layer. The metal layer, adhesion barrier layer, and stress-reducing barrier layer define an interconnect metal stack. Recesses are defined in the interconnect metal stack to expose the dielectric layer. The recesses are filled with a dielectric material, wherein a portion of the interconnect metal stack disposed between adjacent recessed filled with dielectric material defines an interconnect structure.

    Abstract translation: 一种方法包括在形成在基底上的电介质层上形成粘合阻挡层。 第一应力水平存在于粘合阻挡层和电介质层之间的第一界面上。 在粘合阻挡层上方形成有应力降低阻挡层。 所述减小应力的阻挡层减小所述第一应力水平以提供小于所述第一应力水平的第二应力水平，所述第二应力水平穿过所述粘合阻挡层，所述减小应力阻挡层和所述介电层之间的第二界面。 在应力降低阻挡层上形成金属层。 金属层，粘合阻挡层和应力减小阻挡层限定互连金属叠层。 在互连金属叠层中限定凹陷以暴露电介质层。 这些凹部填充有电介质材料，其中设置在相邻凹陷的填充有电介质材料的互连金属叠层的一部分限定互连结构。

    Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product
    8.
    发明授权
    Methods of forming non-continuous conductive layers for conductive structures on an integrated circuit product 有权
    在集成电路产品上形成用于导电结构的非连续导电层的方法

    公开(公告)号：US09059255B2

    公开(公告)日：2015-06-16

    申请号：US13781921

    申请日：2013-03-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vivian W. Ryan ,  Xunyuan Zhang

    IPC: H01L21/768 ,  H01L23/532

    CPC classification number: H01L21/76843 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76868 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a non-continuous layer comprised of a plurality of spaced-apart conductive structures on the layer of insulating material in the trench/via, wherein portions of the layer of insulating material not covered by the plurality of spaced-apart conductive structures remain exposed, forming at least one barrier layer on the non-continuous layer, wherein the barrier layer contacts the spaced-apart conductive structures and the exposed portions of the layer of insulating material, forming at least one liner layer above the barrier layer, and forming a conductive structure in the trench/via above the liner layer.

    Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料层上形成由多个间隔开的导电结构构成的非连续层，其中部分 未被多个间隔开的导电结构覆盖的绝缘材料层保持暴露，在非连续层上形成至少一个阻挡层，其中阻挡层接触间隔开的导电结构和该层的暴露部分 绝缘材料，在阻挡层上形成至少一个衬垫层，以及在衬里层上方的沟槽/通孔中形成导电结构。

    MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES
    9.
    发明申请
    MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES 审中-公开
    用于互连结构的多层障碍层堆叠

    公开(公告)号：US20140264876A1

    公开(公告)日：2014-09-18

    申请号：US14287533

    申请日：2014-05-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC: H01L23/532 ,  H01L23/00

    CPC classification number: H01L23/53209 ,  H01L21/02697 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess.

    Abstract translation: 半导体器件包括限定在介电层中的凹部和限定在凹部中的互连结构。 所述互连结构包括衬在所述凹部中的第一阻挡层，所述第一阻挡层包括钽合金和除了钽之外的第一过渡金属，其中所述第一阻挡层和所述介电层之间的第一界面具有第一应力水平。 第二阻挡层位于第一阻挡层上，第二阻挡层包括钽和氮化钽中的至少一个，其中第二阻挡层和第一阻挡层之间的第二界面具有小于第二阻挡层的第二应力水平 第一压力水平。 互连结构还包括基本上填充凹部的填充材料。

    MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE
    10.
    发明申请
    MULTI-LAYER BARRIER LAYER FOR INTERCONNECT STRUCTURE 审中-公开
    用于互连结构的多层障碍层

    公开(公告)号：US20140217591A1

    公开(公告)日：2014-08-07

    申请号：US14247375

    申请日：2014-04-08

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vivian W. Ryan ,  Xunyuan Zhang ,  Paul R. Besser

    IPC: H01L23/498

    CPC classification number: H01L23/49866 ,  H01L21/76846 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/49827 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a dielectric layer positioned above a substrate of the semiconductor device and a recess defined in the dielectric layer. An adhesion barrier layer is positioned on and in direct contact with at least the sidewalls of the recess, a barrier layer interface being defined where the adhesion barrier layer directly contacts the dielectric layer. A stress-reducing barrier layer is positioned adjacent to the adhesion barrier layer, wherein the stress-reducing barrier layer is adapted to reduce a stress level across the barrier layer interface from a first stress level to a second stress level that is less than the first stress level. At least one layer of a conductive fill material is positioned over the stress-reducing barrier layer, the at least one layer of the conductive fill material substantially filling the recess.

    Abstract translation: 半导体器件包括位于半导体器件的衬底上方的电介质层和限定在电介质层中的凹部。 粘合阻挡层定位在至少凹部的侧壁上并与其直接接触，限定粘合阻障层直接接触电介质层的阻挡层界面。 应力降低阻挡层定位成与粘附阻挡层相邻，其中应力降低阻挡层适于将穿过阻挡层界面的应力水平从第一应力水平降低到小于第一应力水平的第二应力水平 压力水平。 导电填充材料的至少一层位于应力减小阻挡层上方，导电填充材料的至少一层基本上填充凹部。

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