公开(公告)号：US20200066885A1

公开(公告)日：2020-02-27

申请号：US16106344

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.

公开(公告)号：US10115810B2

公开(公告)日：2018-10-30

申请号：US15437168

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L21/331 ,  H01L29/66 ,  H01L29/737 ,  H01L29/165

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. The device structure further includes an emitter, an intrinsic base that has a first thickness, and an extrinsic base coupled with the intrinsic base. The extrinsic base has a lateral arrangement relative to the intrinsic base and relative to the emitter. The intrinsic base has a vertical arrangement between the emitter and the top surface of the collector. The sidewall of the collector extends laterally to undercut the extrinsic base. The extrinsic base has a second thickness that is greater than a first thickness of the intrinsic base.

公开(公告)号：US10079248B2

公开(公告)日：2018-09-18

申请号：US15355231

申请日：2016-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Mark D. Jaffe ,  John J. Pekarik

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/12 ,  H01L29/06 ,  H01L23/528 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/265 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76838 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5283 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/66477 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78654

Abstract: Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate and into a buried oxide layer of the silicon-on-insulator substrate. The buried oxide layer is laterally etched at the location of the opening to define a cavity in the buried oxide layer. The cavity is located partially beneath a section of the device layer, and the cavity is filled with a semiconductor material to form a body contact. A well is formed in the section of the device layer, and the body contact is coupled with a portion of the well.

公开(公告)号：US20160380067A1

公开(公告)日：2016-12-29

申请号：US14747385

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/423 ,  H01L21/306 ,  H01L29/08 ,  H01L29/732 ,  H01L29/66

CPC classification number: H01L29/0821 ,  H01L21/30608 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.

Abstract translation: 双极结型晶体管的器件结构和制造方法。 发射极层形成在基底层上并被蚀刻以形成器件结构的发射极。 发射极层具有作为发射极层的厚度的函数而变化的元素的浓度。 发射极层的蚀刻速率作为元件的浓度的函数而变化，使得发射极在发射极层的厚度上具有可变的宽度。

公开(公告)号：US20210066474A1

公开(公告)日：2021-03-04

申请号：US16551061

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/737 ,  H01L21/02

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

公开(公告)号：US20170288033A1

公开(公告)日：2017-10-05

申请号：US15626241

申请日：2017-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/732 ,  H01L21/306

CPC classification number: H01L29/0821 ,  H01L21/30608 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.

公开(公告)号：US20160190292A1

公开(公告)日：2016-06-30

申请号：US15061725

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： James W. Adkisson ,  David L. Harame ,  Michael L. Kerbaugh ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/732 ,  H01L29/10 ,  H01L29/737 ,  H01L29/161 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L29/732 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7327 ,  H01L29/7371 ,  H01L29/7378

Abstract: The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.

公开(公告)号：US09236499B2

公开(公告)日：2016-01-12

申请号：US14496285

申请日：2014-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/808 ,  H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  H01L27/06 ,  G06F17/50 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/8086 ,  G06F17/5045 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1058 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/808

Abstract: Junction field-effect transistors and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

Abstract translation: 结场效应晶体管和结型场效应晶体管的设计结构。 结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。 形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。 源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

公开(公告)号：US20210057462A1

公开(公告)日：2021-02-25

申请号：US16544074

申请日：2019-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L27/144 ,  H01L29/04 ,  H01L29/165 ,  H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L31/0312 ,  H01L31/02 ,  H01L31/105 ,  H01L31/18

Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.

公开(公告)号：US10910308B2

公开(公告)日：2021-02-02

申请号：US15975041

申请日：2018-05-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain

IPC: H01L23/52 ,  H01L23/525 ,  H01L21/768 ,  H01L23/00 ,  H01L23/62

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.