公开(公告)号：US20150364570A1

公开(公告)日：2015-12-17

申请号：US14304017

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Cuiqin Xu ,  Isabelle Ferain

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/32 ,  H01L29/6659 ,  H01L29/66628

Abstract: One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.

Abstract translation: 本文公开的一种说明性方法包括进行源极/漏极扩展离子注入以在器件的源极/漏极区域中形成掺杂的延伸注入区域，在源极/漏极区域上执行离子注入工艺 VII材料（例如氟），在进行第VII族材料离子注入工艺之后，在源极/漏极区域上方形成覆盖材料层，并且在覆盖材料层就位的情况下，进行退火处理以形成堆垛层错 在源/漏区。

公开(公告)号：US09178053B2

公开(公告)日：2015-11-03

申请号：US14579122

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Johannes M. van Meer

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L29/36

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/7833

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

Abstract translation: 本文公开的一个示例性器件包括位于栅极结构的相对侧上的有源区域中的多个源极/漏极区域，每个源极/漏极区域在晶体管的栅极长度方向上具有横向宽度，并且多个卤素 区域，其中每个光晕区域位于多个源极/漏极区域中的一个的横向宽度的一部分但不是全部的下方。 本文公开的方法包括在有源区域中形成多个晕轮注入区域，其中每个晕轮植入区域的外边缘与隔离区域的相邻内边缘横向间隔开。

公开(公告)号：US09136330B2

公开(公告)日：2015-09-15

申请号：US13947439

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

Abstract translation: 公开了具有改进的浅沟槽隔离（STI）区域和制造方法的半导体结构。 STI区域包括填充有氧化物的下部分和包括设置在下部分上的高杨氏模量（HYM）衬垫和沟槽侧壁并填充有氧化物的上部部分。 HYM衬垫设置在源 - 漏区附近，用于减少浅沟槽隔离（STI）氧化物中的应力松弛，其具有较低的杨氏模量并且柔软。 因此，HYM衬垫用于增加由嵌入式应力源源极 - 漏极区域施加的所需应力，这增强了载流子迁移率，从而提高了半导体性能。

公开(公告)号：US20150221770A1

公开(公告)日：2015-08-06

申请号：US14686228

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract translation: 提供了用于在器件（例如，鳍式场效应晶体管器件（FinFET））中实现硅鳍外延生长的方法。 具体地，提供了用于形成用于FinFET器件的一组硅散热片的方法，所述FinFET器件包括：在衬底上形成的一组栅极结构，所述一组栅极结构中的每一个包括覆盖层和一组间隔物; 在该组栅极结构上形成的氧化物填充物; 通过从所述一组或多组所述栅极结构中去除所述覆盖层和所述一组间隔物而在所述器件中形成的一组开口; 外延生长在器件中的开口组内然后平坦化的硅材料; 并且其中蚀刻氧化物填充物以暴露硅材料并形成该组散热片。

公开(公告)号：US09034737B2

公开(公告)日：2015-05-19

申请号：US13956475

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract translation: 提供了用于在器件（例如，鳍式场效应晶体管器件（FinFET））中实现硅鳍外延生长的方法。 具体地，提供了用于形成用于FinFET器件的一组硅散热片的方法，所述FinFET器件包括：在衬底上形成的一组栅极结构，所述一组栅极结构中的每一个包括覆盖层和一组间隔物; 在该组栅极结构上形成的氧化物填充物; 通过从所述一组或多组所述栅极结构中去除所述覆盖层和所述一组间隔物而在所述器件中形成的一组开口; 外延生长在器件中的开口组内然后平坦化的硅材料; 并且其中蚀刻氧化物填充物以暴露硅材料并形成该组散热片。

公开(公告)号：US08962441B2

公开(公告)日：2015-02-24

申请号：US13927932

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Johannes M. van Meer

IPC: H01L21/76 ,  H01L21/8242 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/70 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/7833

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

公开(公告)号：US09231079B1

公开(公告)日：2016-01-05

申请号：US14304017

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Cuiqin Xu ,  Isabelle Ferain

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/324 ,  H01L21/266

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/32 ,  H01L29/6659 ,  H01L29/66628

Abstract: One illustrative method disclosed herein includes, among other things, performing a source/drain extension ion implantation to form a doped extension implant region in the source/drain regions of the device, performing an ion implantation process on the source/drain regions with a Group VII material (e.g., fluorine), after performing the Group VII material ion implantation process, forming a capping material layer above the source/drain regions, and, with the capping material layer in position, performing an anneal process so as to form stacking faults in the source/drain regions.

Abstract translation: 本文公开的一种说明性方法包括进行源极/漏极扩展离子注入以在器件的源极/漏极区域中形成掺杂的延伸注入区域，在源极/漏极区域上执行离子注入工艺 VII材料（例如氟），在进行第VII族材料离子注入工艺之后，在源极/漏极区域上方形成覆盖材料层，并且在覆盖材料层就位的情况下，进行退火处理以形成堆垛层错 在源/漏区。

公开(公告)号：US20150348830A1

公开(公告)日：2015-12-03

申请号：US14824361

申请日：2015-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

公开(公告)号：US20150001640A1

公开(公告)日：2015-01-01

申请号：US13927932

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Johannes M. van Meer

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/7833

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

公开(公告)号：US09437740B2

公开(公告)日：2016-09-06

申请号：US14686228

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.