公开(公告)号：US10020202B2

公开(公告)日：2018-07-10

申请号：US15099641

申请日：2016-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Donghun Kang ,  Balaji Kannan ,  Jinping Liu

IPC: H01L21/308 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306

CPC classification number: H01L21/3085 ,  H01L21/28556 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

Abstract: A method of fabricating multi Vth devices and the resulting device are disclosed. Embodiments include forming a high-k dielectric layer over a substrate; forming a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second region; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

公开(公告)号：US20160163814A1

公开(公告)日：2016-06-09

申请号：US14563009

申请日：2014-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Takashi Ando ,  Balaji Kannan ,  Vijay Narayanan

IPC: H01L29/49 ,  H01L21/28

CPC classification number: H01L21/823828 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66871

Abstract: A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a titanium-aluminum-carbon-oxygen (TiAlCO) layer.

Abstract translation: 形成晶体管器件的方法包括在衬底上形成界面层和电介质层; 以及在所述电介质层上形成功函数金属层，所述功函数金属层包含钛 - 铝 - 碳 - 氧（TiAlCO）层。

公开(公告)号：US10658363B2

公开(公告)日：2020-05-19

申请号：US16562481

申请日：2019-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Ayse M. Ozbek ,  Tao Chu ,  Bala Haran ,  Vishal Chhabra ,  Katsunori Onishi ,  Guowei Xu

IPC: H01L27/092 ,  H01L29/06 ,  H01L27/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/11

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cut inside a replacement metal gate trench to mitigate n-p proximity effects and methods of manufacture. The structure described herein includes: a first device; a second device, adjacent to the first device; a dielectric material, of the first device and the second device, including a cut within a trench between the first device and the second device; and a common gate electrode shared with the first device and the second device, the common gate electrode provided over the dielectric material and contacting underlying material within the cut.

公开(公告)号：US20200091005A1

公开(公告)日：2020-03-19

申请号：US16134708

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Balaji Kannan ,  Shesh Mani Pandey ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

公开(公告)号：US09748145B1

公开(公告)日：2017-08-29

申请号：US15055826

申请日：2016-02-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Balaji Kannan ,  Unoh Kwon ,  Siddarth Krishnan ,  Takashi Ando ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L21/324 ,  H01L21/225 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518

Abstract: Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region.

公开(公告)号：US10727133B2

公开(公告)日：2020-07-28

申请号：US16134708

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Balaji Kannan ,  Shesh Mani Pandey ,  Haiting Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

公开(公告)号：US10062618B2

公开(公告)日：2018-08-28

申请号：US14721402

申请日：2015-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Aritra Dasgupta ,  Balaji Kannan ,  Unoh Kwon

IPC: H01L27/11 ,  H01L21/8238 ,  H01L21/324 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823857 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/105 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Embodiments of the present invention provide a process that maintains a “keep cap” metal nitride layer on PFET devices within a CMOS structure. The keep cap metal nitride layer is in place while an N-type work function metal is formed on the NFET devices within the CMOS structure. A sacrificial rare earth oxide layer, such as a lanthanum oxide layer is used to facilitate removal of the n-type work function metal selective to the keep cap metal nitride layer.

公开(公告)号：US09741720B1

公开(公告)日：2017-08-22

申请号：US15219967

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shahab Siddiqui ,  Balaji Kannan ,  Siddarth Krishnan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L27/0924 ,  H01L21/0228 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure includes a semiconductor substrate, n-type and p-type FinFETs on the substrate, each of the n-type and the p-type FinFETs include a channel region and a gate structure surrounding the channel region, each gate structure having a phase-changed high-k gate dielectric layer lining a gate trench thereof, the gate trench defined by a pair of spacers. The semiconductor structure further includes a conformal dielectric capping layer over each phase-changed high-k gate dielectric layer, the conformal dielectric capping layer having a higher dielectric constant than the phase-changed high-k gate dielectric layer. Further included on the n-type FinFETs is a multi-layer replacement gate stack of n-type work function material over the phase-changed high-k gate dielectric layer. A method of fabricating the semiconductor structure is also provided.

公开(公告)号：US09418995B2

公开(公告)日：2016-08-16

申请号：US14513725

申请日：2014-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balaji Kannan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/02192 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/2255 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517

Abstract: Embodiments of the present invention provide CMOS structures and methods of gate formation that combine a keep-cap scheme in which a protective layer is maintained on a PFET during a replacement metal gate process that utilizes an NFET-first process flow. Selective nitridation is used to provide nitrogen to the NFET while the PFET is protected from nitrogen by the keep-cap. Additional dopants are provided to the NFET using a gate stack dopant material (GSDM) layer.

Abstract translation: 本发明的实施例提供了CMOS结构和栅极形成方法，其组合了在利用NFET第一工艺流程的替换金属栅极工艺期间在PFET上保持保护层的保持帽方案。 选择性氮化用于向NFET提供氮气，同时PFET通过保护盖被氮保护。 使用栅极堆叠掺杂剂材料（GSDM）层向NFET提供附加的掺杂剂。

公开(公告)号：US10741668B2

公开(公告)日：2020-08-11

申请号：US15654234

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bala Haran ,  Ruilong Xie ,  Balaji Kannan ,  Katsunori Onishi ,  Vimal K. Kamineni

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/161 ,  H01L21/285 ,  H01L29/78 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to replacement metal gate structures and methods of manufacture. The structure includes at least one short channel device including a dielectric material, a workfunction metal, and a capping material, and a long channel device comprising the dielectric material, the workfunction metal and fluorine free gate conductor material.