公开(公告)号：US20130146898A1

公开(公告)日：2013-06-13

申请号：US13740734

申请日：2013-01-14

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Kevin Sean Matocha ,  Gregory Keith Dudoff ,  William Gregg Hawkins ,  Zachary Matthew Stum ,  Stephen Daley Arthur ,  Dale Marius Brown

IPC: H01L29/49

CPC classification number: H01L29/4975 ,  H01L21/0465 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7827 ,  H01L29/872

Abstract: The present application provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 μm. A vertical SiC MOSFET is also provided.

Abstract translation: 本申请提供了制造金属氧化物半导体场效应晶体管的方法。 该方法包括以下步骤：在碳化硅层上形成源极区域并退火源极区域。 在源区和碳化硅层上形成栅氧化层。 该方法还包括在栅极氧化物层上设置栅电极，并在栅电极和栅极氧化物层上设置电介质层。 该方法还包括蚀刻介电层的一部分和栅极氧化物层的一部分以在栅电极上形成侧壁。 金属层设置在栅电极，侧壁和源极区上。 该方法还包括通过使金属层经受至少约800℃的温度来形成栅极接触和源极接触。栅极接触和源极接触包括金属硅化物。 栅极触点与源极之间的距离小于0.6μm。 还提供了一个垂直的SiC MOSFET。

公开(公告)号：US11417759B2

公开(公告)日：2022-08-16

申请号：US16433809

申请日：2019-06-06

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Joseph Darryl Michael ,  Tammy Lynn Johnson ,  David Alan Lilienfeld ,  Kevin Sean Matocha ,  Jody Alan Fronheiser ,  William Gregg Hawkins

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/45 ,  H01L29/16 ,  H01L29/49 ,  H01L29/739 ,  H01L29/745 ,  H01L23/04 ,  H01L21/50

Abstract: According to one embodiment, a semiconductor device, having a semiconductor substrate comprising silicon carbide with a gate electrode disposed on a portion of the substrate on a first surface with, a drain electrode disposed on a second surface of the substrate. There is a dielectric layer disposed on the gate electrode and a remedial layer disposed about the dielectric layer, wherein the remedial layer is configured to mitigate negative bias temperature instability maintaining a change in threshold voltage of less than about 1 volt. A source electrode is disposed on the remedial layer, wherein the source electrode is electrically coupled to a contact region of the semiconductor substrate.

公开(公告)号：US10937869B2

公开(公告)日：2021-03-02

申请号：US16147227

申请日：2018-09-28

Applicant: General Electric Company

Inventor： William Gregg Hawkins ,  Reza Ghandi ,  Christopher Bauer ,  Shaoxin Lu

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L21/306 ,  H01L21/04 ,  H01L21/02 ,  H01L29/423

Abstract: The subject matter disclosed herein relates to wide band gap semiconductor power devices and, more specifically, to high-energy implantation masks used in forming silicon carbide (SiC) power devices, such as charge balanced (CB) SiC power devices. An intermediate semiconductor device structure includes a SiC substrate layer having a first conductivity type and silicon carbide (SiC) epitaxial (epi) layer having the first conductivity type disposed on the SiC substrate layer. The intermediate device structure also includes a silicon high-energy implantation mask (SiHEIM) disposed directly on a first portion of the SiC epi layer and having a thickness between 5 micrometers (μm) and 20 μm. The SiHEIM is configured to block implantation of the first portion of the SiC epi layer during a high-energy implantation process having an implantation energy greater than 500 kiloelectron volts (keV).