公开(公告)号：US20110045171A1

公开(公告)日：2011-02-24

申请号：US12544110

申请日：2009-08-19

申请人： Fenton Read McFeely ,  Chih-Chao Yang ,  John Jcobs Yurkas

发明人： Fenton Read McFeely ,  Chih-Chao Yang ,  John Jcobs Yurkas

IPC分类号： B05D5/12

CPC分类号： C23C16/16 ,  C23C16/04 ,  C23C16/56 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/76849 ,  H01L21/7685

摘要： Techniques for forming a ruthenium (Ru) capping layer on a copper (Cu) wire are provided. In one aspect, a method of forming a Ru capping layer on at least one exposed surface of a Cu wire embedded in a dielectric structure includes the following steps. A first Ru layer is selectively deposited onto the Cu wire and the dielectric structure by chemical vapor deposition (CVD) for a period of time during which selective nucleation of the Ru occurs on the surface of the Cu wire. Any nucleated Ru present on the dielectric structure is oxidized. The oxidized Ru and an aqueous acid are contacted to remove the oxidized Ru from the dielectric structure based on a selectivity of the aqueous acid in dissolving the oxidized Ru. A second Ru layer is selectively deposited onto the first Ru layer by CVD to produce a thicker Ru layer. The steps of oxidizing and contacting the oxidized Ru and an aqueous acid are repeated until a Ru layer having a thickness that is suitable for use as a Ru capping layer on at least one exposed surface of the Cu wire embedded in the dielectric structure is achieved.

摘要翻译： 提供了在铜（Cu）线上形成钌（Ru）覆盖层的技术。 一方面，在嵌入电介质结构的Cu线的至少一个露出表面上形成Ru覆盖层的方法包括以下步骤。 通过化学气相沉积（CVD）在Cu线和电介质结构上选择性地将第一Ru层沉积在Cu线的表面上发生Ru的选择性成核的一段时间。 存在于电介质结构上的任何成核Ru被氧化。 接触氧化的Ru和酸水以从介电结构中除去氧化的Ru，这是基于酸水溶解氧化Ru的选择性。 通过CVD将第二Ru层选择性地沉积到第一Ru层上以产生更厚的Ru层。 重复氧化和接触氧化的Ru和酸性水的步骤，直到达到在埋入电介质结构的Cu线的至少一个暴露表面上适合用作Ru覆盖层的厚度的Ru层。

公开(公告)号：US08661664B2

公开(公告)日：2014-03-04

申请号：US12838597

申请日：2010-07-19

申请人： Fenton Read McFeely ,  Chih-Chao Yang

发明人： Fenton Read McFeely ,  Chih-Chao Yang

IPC分类号： H01K3/10

CPC分类号： H05K1/09 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

摘要： Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.

摘要翻译： 提供了提高铜（Cu）填充通孔电导率的技术。 一方面，提供了制造填充铜的通孔的方法。 该方法包括以下步骤。 在电介质中蚀刻通孔。 通孔内有一个扩散屏障。 薄的钌（Ru）层共形沉积到扩散阻挡层上。 在Ru层上沉积薄的种子Cu层。 进行第一退火以增加种子Cu层的晶粒尺寸。 通孔填充有额外的铜。 进行第二次退火以增加附加Cu的晶粒尺寸。

公开(公告)号：US20120205804A1

公开(公告)日：2012-08-16

申请号：US13025322

申请日：2011-02-11

申请人： Fenton Read McFeely ,  Chih-Chao Yang

发明人： Fenton Read McFeely ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

摘要翻译： 提供了高纯铜（Cu）填充线和通孔的技术形成。 在一个方面，提供了一种制造填充有高纯度铜的管线和通孔的方法。 该方法包括以下步骤。 在电介质中蚀刻通孔。 通孔内有一个扩散屏障。 薄的钌（Ru）层共形沉积到扩散阻挡层上。 通过溅射工艺在Ru层上沉积Cu层。 进行回流退火以消除管线和通孔中的空隙。

公开(公告)号：US20120012372A1

公开(公告)日：2012-01-19

申请号：US12838597

申请日：2010-07-19

申请人： Fenton Read McFeely ,  Chih-Chao Yang

发明人： Fenton Read McFeely ,  Chih-Chao Yang

IPC分类号： H05K1/09 ,  H01B13/00

CPC分类号： H05K1/09 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

摘要： Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.

摘要翻译： 提供了提高铜（Cu）填充通孔电导率的技术。 一方面，提供一种制造填充铜的通孔的方法。 该方法包括以下步骤。 在电介质中蚀刻通孔。 通孔内有一个扩散屏障。 薄的钌（Ru）层共形沉积到扩散阻挡层上。 在Ru层上沉积薄的种子Cu层。 进行第一退火以增加种子Cu层的晶粒尺寸。 通孔填充有额外的铜。 进行第二次退火以增加附加Cu的晶粒尺寸。

公开(公告)号：US09048296B2

公开(公告)日：2015-06-02

申请号：US13025322

申请日：2011-02-11

申请人： Fenton Read McFeely ,  Chih-Chao Yang

发明人： Fenton Read McFeely ,  Chih-Chao Yang

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

摘要翻译： 提供了高纯铜（Cu）填充线和通孔的技术形成。 在一个方面，提供了一种制造填充有高纯度铜的管线和通孔的方法。 该方法包括以下步骤。 在电介质中蚀刻通孔。 通孔内有一个扩散屏障。 薄的钌（Ru）层共形沉积到扩散阻挡层上。 通过溅射工艺在Ru层上沉积Cu层。 进行回流退火以消除管线和通孔中的空隙。

公开(公告)号：US20110052797A1

公开(公告)日：2011-03-03

申请号：US12548269

申请日：2009-08-26

申请人： Fenton Read McFeely ,  Chih-Chao Yang ,  John Jacob Yurkas

发明人： Fenton Read McFeely ,  Chih-Chao Yang ,  John Jacob Yurkas

IPC分类号： B05D5/12

CPC分类号： C23C8/24 ,  C23C8/80

摘要： Techniques for nitridation of copper (Cu) wires. In one aspect, a method for nitridation of a Cu wire is provided. The method includes the following step. The Cu wire and trimethylsilylazide (TMSAZ) in a carrier gas are contacted at a temperature, pressure and for a length of time sufficient to form a nitridized layer on one or more surfaces of the Cu wire. The Cu wire can be part of a wiring structure and can be embedded in a dielectric media. The dielectric media can comprise an ultra low-k dielectric media.

摘要翻译： 铜（Cu）线的氮化技术。 在一方面，提供了一种用于氮化Cu丝的方法。 该方法包括以下步骤。 载气中的Cu线和三甲基甲硅烷基叠氮化物（TMSAZ）在足以在Cu线的一个或多个表面上形成氮化层的温度和压力下接触。 Cu线可以是布线结构的一部分，并且可以嵌入介电介质中。 电介质介质可以包括超低k电介质介质。

公开(公告)号：US09620619B2

公开(公告)日：2017-04-11

申请号：US13348894

申请日：2012-01-12

申请人： Veeraraghavan S. Basker ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Veeraraghavan S. Basker ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/20 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/78

摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

公开(公告)号：US09059254B2

公开(公告)日：2015-06-16

申请号：US13604660

申请日：2012-09-06

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

公开(公告)号：US08957519B2

公开(公告)日：2015-02-17

申请号：US12910075

申请日：2010-10-22

申请人： Chih-Chao Yang ,  Hsueh-Chung Chen

发明人： Chih-Chao Yang ,  Hsueh-Chung Chen

IPC分类号： H01L23/48 ,  H01L21/321 ,  H01L21/02 ,  H01L21/768

CPC分类号： H01L21/321 ,  H01L21/02304 ,  H01L21/76852 ,  H01L21/76886

摘要： The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas.

摘要翻译： 可以通过在沉积这种电介质之前在这种金属结构的暴露表面上形成粘合层来解决图案化金属结构上的电介质涂层粘附性差的问题。 根据一个实施例，本发明提供了一种通过将金属结构暴露于受控气氛和含氮气体的流动来在集成电路内的金属互连结构的表面上形成自对准粘附层的方法。

公开(公告)号：US08889546B2

公开(公告)日：2014-11-18

申请号：US13600773

申请日：2012-08-31

申请人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu ,  Surbhi Mittal

发明人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu ,  Surbhi Mittal

IPC分类号： H01L21/4763 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/02362 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.

摘要翻译： 提供一种制造互连结构的方法，其包括提供具有约3.0或更小介电常数的介电材料和嵌入其中的至少一种导电材料，所述至少一种导电材料具有与上表面共面的上表面 的介电材料; 并且在所述至少一种导电材料的上表面上直接形成含贵金属的帽，其中所述贵金属帽是不连续的或不均匀的。