公开(公告)号：US20180061951A1

公开(公告)日：2018-03-01

申请号：US15632939

申请日：2017-06-26

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shoji KITAMURA

IPC分类号： H01L29/16 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/1608 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7839 ,  H01L29/872

摘要： A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a silicon carbide semiconductor substrate of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the second conductivity type, connected with the first semiconductor region; a first electrode forming a Schottky contact with a first semiconductor layer and a first semiconductor region; and a second electrode forming an ohmic contact with the second semiconductor region. A density of the second electrode is lower at a center portion of the silicon carbide semiconductor substrate and increases toward an outer peripheral side.

公开(公告)号：US20170084701A1

公开(公告)日：2017-03-23

申请号：US15367065

申请日：2016-12-01

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shoji KITAMURA

IPC分类号： H01L29/16 ,  H01L29/36 ,  H01L29/872 ,  H01L29/06

CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/8611 ,  H01L29/872

摘要： In an edge termination structure portion, first and second JTE regions are disposed concentrically surrounding an active region. Between the first and second JTE regions, a p-type electric field relaxation region is disposed that includes a first subregion and a second subregion alternately and repeatedly arranged concentrically surround a periphery of the first JTE region. An average impurity concentration of the electric field relaxation region is higher that the impurity concentration of the first JTE region adjacent on the inner side and lower than the impurity concentration of the second JTE region adjacent on the outer side. First subregions have widths that decrease the farther outward they are arranged. Second subregions have widths that are substantially the same independent of position. The first subregions and the first JTE region have equal impurity concentrations. The second subregions and the second JTE region have equal impurity concentrations.

公开(公告)号：US20160307993A1

公开(公告)日：2016-10-20

申请号：US15197821

申请日：2016-06-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hidenao KURIBAYASHI ,  Shoji KITAMURA ,  Yuichi ONOZAWA

IPC分类号： H01L29/06 ,  H01L27/06 ,  H01L21/324 ,  H01L29/78 ,  H01L21/22 ,  H01L21/265

CPC分类号： H01L29/1095 ,  H01L21/221 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0619 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/868 ,  H01L29/872

摘要： A defective layer is formed by ion implanting argon for a p+ anode layer from a front surface side of a base substrate. Here, the range of the argon is set to be shallower than the diffusion depth of the p+ anode layer such that platinum atoms are localized in an electron entering region near a pn junction of the p+ anode layer with an n− drift layer at a platinum diffusion step executed later. The platinum atoms in a platinum paste applied to the back surface of the base substrate are thereafter diffused in the p+ anode layer to be localized on a cathode side of the defective layer.

摘要翻译： 通过从基底的前表面侧离子注入用于p +阳极层的氩形成缺陷层。 这里，将氩的范围设定为比p +阳极层的扩散深度浅，使得铂原子位于p +阳极层的pn结附近的电子入射区域和位于铂的n漂移层 扩散步骤稍后执行。 然后施加到基底衬底的背面的铂糊料中的铂原子扩散到p +阳极层中，以定位在缺陷层的阴极侧。

公开(公告)号：US20140070369A1

公开(公告)日：2014-03-13

申请号：US13962218

申请日：2013-08-08

申请人： Fuji Electric Co., Ltd.

发明人： Shoji KITAMURA

IPC分类号： H01L29/36 ,  H01L21/22

CPC分类号： H01L29/868 ,  H01L21/22 ,  H01L21/221 ,  H01L21/225 ,  H01L21/263 ,  H01L21/3105 ,  H01L21/31111 ,  H01L29/063 ,  H01L29/36 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66204 ,  H01L29/861

摘要： A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n− type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n− type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n− type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n− type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n− type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.

摘要翻译： 简化的制造工艺稳定地生产具有高电特性的半导体器件，其中铂作为受体。 等离子体处理破坏了沉积在n +型半导体衬底上的n型漂移层上形成的氧化物膜的表面。 图案化氧化膜以具有锥形末端。 在以氧化膜为掩模的n型漂移层上进行两个质子照射，以在n型漂移层的表面附近形成点缺陷区域。 将含有1重量％铂的二氧化硅浆料施加到未被氧化物膜覆盖的n型漂移层表面的露出区域。 热处理使n型漂移层的表面附近由接受体的铂原子反转成p型。 p型反转增强区域形成p型阳极区域。

公开(公告)号：US20160372540A1

公开(公告)日：2016-12-22

申请号：US15250998

申请日：2016-08-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shoji KITAMURA

IPC分类号： H01L29/06 ,  H01L29/872 ,  H01L29/16

CPC分类号： H01L29/0619 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/872

摘要： A semiconductor device, including a substrate of a first conductivity type, an active region and a termination structure portion formed on a front surface of the substrate, and a plurality of regions of a second conductivity type formed concentrically surrounding the periphery of the active region in the termination structure portion. Each region has a higher impurity concentration than one of the regions adjacent thereto on an outside thereof. The plurality regions include first and second semiconductor regions, and an intermediate region sandwiched between, and in contact with, the first and second semiconductor regions. The intermediate region includes a plurality of first subregions and a plurality of second subregions that are alternately arranged along a path in parallel to a boundary between the active region and the termination structure portion, the second subregions having a lower impurity concentration than the first subregions.

摘要翻译： 一种半导体器件，包括第一导电类型的衬底，形成在衬底的前表面上的有源区和端接结构部分，以及多个第二导电类型的区域，其形成为同心地围绕有源区的周边 端接结构部分。 每个区域在其外部具有比与其相邻的区域中的一个更高的杂质浓度。 多个区域包括第一和第二半导体区域以及夹在第一和第二半导体区域之间并与第一和第二半导体区域接触的中间区域。 中间区域包括多个第一子区域和多个第二子区域，其沿着平行于有源区域和端接结构部分之间的边界的路径交替布置，第二子区域具有比第一子区域更低的杂质浓度。

公开(公告)号：US20160254148A1

公开(公告)日：2016-09-01

申请号：US15027423

申请日：2014-09-26

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shoji KITAMURA

IPC分类号： H01L21/02 ,  H01L21/04 ,  H01L29/66 ,  H01L29/16 ,  H01L29/32 ,  H01L29/47 ,  H01L29/872 ,  H01L21/265

CPC分类号： H01L21/02529 ,  H01L21/02378 ,  H01L21/02675 ,  H01L21/02689 ,  H01L21/046 ,  H01L21/0495 ,  H01L21/26506 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/872

摘要： A method of manufacturing a silicon carbide semiconductor device in which a first-conductivity-type silicon carbide semiconductor epitaxial layer is formed on a main surface of a first-conductivity-type silicon carbide semiconductor substrate, wherein the silicon carbide semiconductor device manufacturing method includes: a step for supplying strain energy to at least one of (i) a surface layer of the surface of the silicon carbide semiconductor substrate on which the silicon carbide semiconductor epitaxial layer is formed, and (ii) the surface of the silicon carbide semiconductor epitaxial layer, a step for forming a carbon film on the surface layer, and a step for forming a recrystallized layer by adding a heat treatment for recrystallizing the surface layer to which the strain energy is supplied.

摘要翻译： 一种制造在第一导电型碳化硅半导体衬底的主表面上形成第一导电型碳化硅半导体外延层的碳化硅半导体器件的方法，其中所述碳化硅半导体器件制造方法包括： 向（i）形成有碳化硅半导体外延层的碳化硅半导体衬底的表面的表面层中的至少一个提供应变能的步骤，以及（ii）碳化硅半导体外延层的表面 ，在表面层上形成碳膜的工序，以及通过对供给应变能的表面层进行再结晶的热处理而形成再结晶层的工序。

公开(公告)号：US20130113497A1

公开(公告)日：2013-05-09

申请号：US13671706

申请日：2012-11-08

申请人： FUJI ELECTRIC CO., LTD.

发明人： Katsunori SUZUKI ,  Akihiko OHI ,  Shoji KITAMURA ,  Takahiro OOYAMA

IPC分类号： G01R31/08

CPC分类号： G01R31/311

摘要： A fault position analysis method and a fault position analysis device for a semiconductor device, through which a fault position of a SiC semiconductor device can be analyzed and specified by an OBI RCH method, are disclosed. The fault position analysis method for the semiconductor device scans and irradiates a device and a circuit on a front surface of a substrate with a laser beam from a rear surface side of the substrate of the semiconductor device to heat the device and the circuit. It causes a current to flow to the device and the circuit while being heated, detects a change in a resistance value caused by a change in a current, and analyzes the fault position. The semiconductor device is a semiconductor device which uses an N-doped SiC substrate. Laser beams having wavelengths of 650 to 810 nm are used.

摘要翻译： 公开了一种通过OBI RCH方法分析和指定SiC半导体器件的故障位置的半导体器件的故障位置分析方法和故障位置分析装置。 半导体器件的故障位置分析方法利用来自半导体器件的衬底的后表面侧的激光束来扫描并照射衬底前表面上的器件和电路，以加热器件和电路。 电流在加热时流向设备和电路，检测由电流变化引起的电阻值的变化，分析故障位置。 半导体器件是使用N掺杂的SiC衬底的半导体器件。 使用波长为650〜810nm的激光束。

公开(公告)号：US20220037462A1

公开(公告)日：2022-02-03

申请号：US17496586

申请日：2021-10-07

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shoji KITAMURA

IPC分类号： H01L29/06 ,  H01L29/872 ,  H01L29/16

摘要： A semiconductor device, including a substrate of a first conductivity type, an active region and a termination structure portion formed on a front surface of the substrate, and a plurality of regions of a second conductivity type formed concentrically surrounding the periphery of the active region in the termination structure portion. Each region has a higher impurity concentration than one of the regions adjacent thereto on an outside thereof. The plurality regions include first and second semiconductor regions, and an intermediate region sandwiched between, and in contact with, the first and second semiconductor regions, and a third semiconductor region. The intermediate region includes a plurality of first subregions and a plurality of second subregions that are alternately arranged along a path in parallel to a boundary between the active region and the termination structure portion, the second subregions having a lower impurity concentration than the first subregions.

公开(公告)号：US20200227261A1

公开(公告)日：2020-07-16

申请号：US16835263

申请日：2020-03-30

申请人： FUJI ELECTRIC CO., LTD.

发明人： Katsushi NISHIYAMA ,  Masayuki MIYAZAKI ,  Shoji KITAMURA

IPC分类号： H01L21/04 ,  H01L29/36 ,  H01L29/66

摘要： To enhance efficiency of a process of implanting impurities into a silicon carbide semiconductor layer. To provide a method of manufacturing a semiconductor device including a silicon carbide semiconductor layer, the method of manufacturing including: implanting impurities multiple times to an impurity implantation region in the silicon carbide semiconductor layer to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or lower than 150° C. In the implanting, impurities may be implanted multiple times to the impurity implantation region to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or higher than room temperature.

公开(公告)号：US20190305089A1

公开(公告)日：2019-10-03

申请号：US16446043

申请日：2019-06-19

申请人： FUJI ELECTRIC CO., LTD.

发明人： Shoji KITAMURA

IPC分类号： H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/36 ,  H01L21/04 ,  H01L29/872

摘要： In an edge termination structure portion, first and second JTE regions are disposed concentrically surrounding an active region. Between the first and second JTE regions, a p-type electric field relaxation region is disposed that includes a first subregion and a second subregion alternately and repeatedly arranged concentrically surround a periphery of the first JTE region. An average impurity concentration of the electric field relaxation region is higher that the impurity concentration of the first JTE region adjacent on the inner side and lower than the impurity concentration of the second JTE region adjacent on the outer side. First subregions have widths that decrease the farther outward they are arranged. Second subregions have widths that are substantially the same independent of position. The first subregions and the first JTE region have equal impurity concentrations. The second subregions and the second JTE region have equal impurity concentrations.