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    Phase shifter for linearly shifting phase of input signal based on phase control signals
    1.
    发明授权
    Phase shifter for linearly shifting phase of input signal based on phase control signals 有权

    公开(公告)号：US12224728B2

    公开(公告)日：2025-02-11

    申请号：US18182571

    申请日：2023-03-13

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Seon-Ho Han ,  Bon Tae Koo

    IPC: H03H11/18 ,  H03H11/20

    Abstract: Disclosed is a phase shift circuit including an input circuit for generating first to fourth internal signals based on an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal and a switching circuit for outputting first to fourth shift signals based on the first to fourth internal signals. The input circuit includes a first transistor connected between a ground node and a first node to operate based on the in-phase signal and the first bias signal, a second transistor connected between the ground node and a second node to operate based on the complementary in-phase signal and the first bias signal, a third transistor connected between the ground node and the first node to operate based on the second bias signal, and a fourth transistor connected between the ground node and the second node to operate based on the second bias signal.

    Digital clock and data recovery circuit and feedback loop circuit including the same
    2.
    发明授权
    Digital clock and data recovery circuit and feedback loop circuit including the same 有权

    公开(公告)号：US12113887B2

    公开(公告)日：2024-10-08

    申请号：US17881417

    申请日：2022-08-04

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Seon-Ho Han ,  Young-Su Kwon

    IPC: H04L7/033 ,  H03L7/08 ,  H03L7/093

    CPC classification number: H04L7/033 ,  H03L7/0807 ,  H03L7/093

    Abstract: Disclosed are a digital CDR circuit and a feedback loop circuit including the same. The digital CDR circuit includes a phase detector that receives an input signal and outputs a phase detection result signal corresponding to a determination result for a sampling time based on the input signal, a charge pump that receives the phase detection result signal and outputs an amplified signal obtained by multiplying the phase detection result signal by a gain, a loop filter that receives the amplified signal and filters the amplified signal to output a filtered signal, and a phase shift control code generator that generates a control signal for controlling a phase of a signal based on the filtered signal, and the input signal includes plural data signals and plural error signals, and the data signals and the error signals are digital signals which are quantized based on a signal magnitude.

    Phase array receiver
    3.
    发明授权
    Phase array receiver 有权

    公开(公告)号：US10367569B2

    公开(公告)日：2019-07-30

    申请号：US15921424

    申请日：2018-03-14

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Seon-Ho Han ,  Bon Tae Koo

    IPC: H04B7/08 ,  H04B1/16 ,  H03F3/19 ,  H03F3/45 ,  H03D7/14 ,  H01Q3/42 ,  H03G3/30 ,  H01Q3/36 ,  H03D7/16

    Abstract: Provided is a phase array receiver. A phase array receiver according to an embodiment of the present invention includes a plurality of antennas, a plurality of low-noise amplifiers, a plurality of phase shifters, a plurality of transconductors, and a frequency mixer. A plurality of low-noise amplifiers amplify RF signals received from the plurality of antennas. The plurality of phase shifters adjusts the phase of the RF signals to generate a plurality of RF phase adjustment signals. The plurality of transconductors convert a plurality of RF phase adjustment signals into a plurality of RF current signals based on the gain control signal. The frequency mixer converts a sum of the plurality of RF current signals into a mixed current signal. According to the inventive concept, the linearity of the signal processing may be improved and the area for the implementation of the phase array receiver may be reduced.

    Subsampling receiver using interstage off-chip RF band pass filter
    4.
    发明授权
    Subsampling receiver using interstage off-chip RF band pass filter 有权
    子采样接收机采用片间片外RF带通滤波器

    公开(公告)号：US09209844B2

    公开(公告)日：2015-12-08

    申请号：US13737726

    申请日：2013-01-09

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Seon-Ho Han ,  Hyun Kyu Yu

    IPC: H04B1/10 ,  H04B1/22 ,  H04B1/06 ,  H04B1/00

    CPC classification number: H04B1/06 ,  H04B1/0014

    Abstract: The inventive concept relates to a wireless communication receiver. The wireless communication receiver includes a second off-chip RF filter, an RF-to-digital converter and a digital pre-processor processing a signal converted into a digital. The RF-to-digital converter converts an RF signal being received into a digital signal of DC frequency band or intermediate frequency band and has a dynamic range that can process a wanted RF band signal and unwanted signals near to the wanted RF band signal. The digital pre-processor digitally controls a signal gain to transmit it to a modulator/demodulator.

    Abstract translation: 本发明构思涉及无线通信接收机。 无线通信接收机包括第二片外RF滤波器，RF到数字转换器和处理转换成数字信号的数字预处理器。 RF-数字转换器将接收的RF信号转换为DC频带或中频带的数字信号，并且具有可处理所需RF频带信号的动态范围和靠近所需RF频带信号的不需要的信号。 数字预处理器以数字方式控制信号增益，将其发送到调制器/解调器。

    ACCUMULATOR AND DATA WEIGHTED AVERAGE DEVICE INCLUDING THE ACCUMULATOR
    6.
    发明申请
    ACCUMULATOR AND DATA WEIGHTED AVERAGE DEVICE INCLUDING THE ACCUMULATOR 有权
    包括累加器的累加器和数据加权平均装置

    公开(公告)号：US20130268572A1

    公开(公告)日：2013-10-10

    申请号：US13854041

    申请日：2013-03-29

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Seon-Ho Han ,  Hyun Kyu Yu

    IPC: G06F17/10

    CPC classification number: G06F17/10 ,  H03M1/0665 ,  H03M1/665 ,  H03M3/464

    Abstract: Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.

    Abstract translation: 公开了一种用于降低数据转换器的非线性的累加器和包括累加器的数据加权平均装置。 根据累加器，包括配置为根据时钟信号输出输入数据的寄存器; 第一加法器，被配置为接收具有任何位宽度的数字输入信号和来自寄存器的输出信号以执行加法运算; 预置单元，被配置为根据第一加法器的进位是否产生预置值或0值; 以及第二加法器，其被配置为接收第一加法器的输出信号和预设单元的输出信号以执行加法运算，并将加法运算输入到寄存器和包括累加器的数据加权平均装置，可以提高 通过生成除了2n个DAC代码之外的多个DAC代码，在数据转换器中发生非线性。

    Accumulator and data weighted average device including the accumulator
    8.
    发明授权
    Accumulator and data weighted average device including the accumulator 有权
    累加器和数据加权平均设备包括累加器

    公开(公告)号：US09378184B2

    公开(公告)日：2016-06-28

    申请号：US13854041

    申请日：2013-03-29

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Seon-Ho Han ,  Hyun Kyu Yu

    IPC: G06F17/10 ,  H03M1/66 ,  H03M3/00

    CPC classification number: G06F17/10 ,  H03M1/0665 ,  H03M1/665 ,  H03M3/464

    Abstract: Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.

    Abstract translation: 公开了一种用于降低数据转换器的非线性的累加器和包括累加器的数据加权平均装置。 根据累加器，包括配置为根据时钟信号输出输入数据的寄存器; 第一加法器，被配置为接收具有任何位宽度的数字输入信号和来自寄存器的输出信号以执行加法运算; 预置单元，被配置为根据第一加法器的进位是否产生预置值或0值; 以及第二加法器，其被配置为接收第一加法器的输出信号和预设单元的输出信号以执行加法运算，并将加法运算输入到寄存器和包括累加器的数据加权平均装置，可以提高 通过生成除了2n个DAC代码之外的多个DAC代码，在数据转换器中发生非线性。

    Phase shifter with function of controlling beam side lobe
    9.
    发明授权
    Phase shifter with function of controlling beam side lobe 有权

    公开(公告)号：US11863126B2

    公开(公告)日：2024-01-02

    申请号：US17327401

    申请日：2021-05-21

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Seon-Ho Han ,  Bon Tae Koo

    IPC: H03D7/14 ,  H03D7/16

    CPC classification number: H03D7/1483 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165

    Abstract: Disclosed is a phase shifter, which includes a signal generator that generates a first signal and a second signal having a phase orthogonal to a phase of the first signal, and outputs the first signal and the second signal, an operator that generates a first current and a second current, and amplifies the first current and the second current, and a signal converter converting a first digital signal and a second digital signal. The operator includes an input circuit converting the first signal and the second signal, a path selection circuit determining paths of the generated first current and the generated second current, and a cascode circuit buffering the first current and the second current. The operator sums the first current and the second current, controls a vector of the first current and a vector of the second current, and generates a voltage signal through an output load.

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