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11 条记录 (耗时 0.021 秒)

    Digital phase-locked loop
    2.
    发明授权
    Digital phase-locked loop 有权
    数字锁相环

    公开(公告)号：US09013216B2

    公开(公告)日：2015-04-21

    申请号：US14028707

    申请日：2013-09-17

    申请人： Electronics and Telecommunications Research Institute

    发明人： Hyun Ho Boo ,  Byung Hun Min ,  Duong Quoc Hoang ,  Cheon Soo Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/06 ,  H03L7/08

    CPC分类号： H03L7/08 ,  H03L7/095

    摘要： Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.

    摘要翻译： 公开了一种数字锁相环，包括：时间数字转换器（TDC），被配置为基于输入时钟和参考时钟输出数字位，其中TDC包括：第一仲裁器组，其被配置为补偿 对于具有第一平均偏移的输入时钟和参考时钟之间的相位差，并输出第一逻辑值; 第二仲裁器组，被配置为用第二平均偏移补偿所述输入时钟和所述参考时钟之间的相位差，并输出第二逻辑值; 以及信号处理器，被配置为基于第一和第二逻辑值输出数字位。

    ACCUMULATOR AND DATA WEIGHTED AVERAGE DEVICE INCLUDING THE ACCUMULATOR
    7.
    发明申请
    ACCUMULATOR AND DATA WEIGHTED AVERAGE DEVICE INCLUDING THE ACCUMULATOR 有权
    包括累加器的累加器和数据加权平均装置

    公开(公告)号：US20130268572A1

    公开(公告)日：2013-10-10

    申请号：US13854041

    申请日：2013-03-29

    申请人： Electronics and Telecommunications Research Institute

    发明人： Seon-Ho Han ,  Hyun Kyu Yu

    IPC分类号： G06F17/10

    CPC分类号： G06F17/10 ,  H03M1/0665 ,  H03M1/665 ,  H03M3/464

    摘要： Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.

    摘要翻译： 公开了一种用于降低数据转换器的非线性的累加器和包括累加器的数据加权平均装置。 根据累加器，包括配置为根据时钟信号输出输入数据的寄存器; 第一加法器，被配置为接收具有任何位宽度的数字输入信号和来自寄存器的输出信号以执行加法运算; 预置单元，被配置为根据第一加法器的进位是否产生预置值或0值; 以及第二加法器，其被配置为接收第一加法器的输出信号和预设单元的输出信号以执行加法运算，并将加法运算输入到寄存器和包括累加器的数据加权平均装置，可以提高 通过生成除了2n个DAC代码之外的多个DAC代码，在数据转换器中发生非线性。

    Accumulator and data weighted average device including the accumulator
    8.
    发明授权
    Accumulator and data weighted average device including the accumulator 有权
    累加器和数据加权平均设备包括累加器

    公开(公告)号：US09378184B2

    公开(公告)日：2016-06-28

    申请号：US13854041

    申请日：2013-03-29

    申请人： Electronics and Telecommunications Research Institute

    发明人： Seon-Ho Han ,  Hyun Kyu Yu

    IPC分类号： G06F17/10 ,  H03M1/66 ,  H03M3/00

    CPC分类号： G06F17/10 ,  H03M1/0665 ,  H03M1/665 ,  H03M3/464

    摘要： Disclosed are an accumulator for reducing nonlinearity of a data converter and a data weighted average device including the accumulator. According to the accumulator including a register configured to output input data according to a clock signal; a first adder configured to receive a digital input signal having any bit width and an output signal from the register to perform an add operation; a preset unit configured to output a preset value or a 0 value according to whether a carry of the first adder is generated; and a second adder configured to receive an output signal of the first adder and an output signal of the preset unit to perform the add operation and input the add operation to the register and the data weighted average device including the accumulator, it is possible to improve the nonlinearity occurring in the data converter by generating a number of DAC codes in addition to 2n DAC codes.

    摘要翻译： 公开了一种用于降低数据转换器的非线性的累加器和包括累加器的数据加权平均装置。 根据累加器，包括配置为根据时钟信号输出输入数据的寄存器; 第一加法器，被配置为接收具有任何位宽度的数字输入信号和来自寄存器的输出信号以执行加法运算; 预置单元，被配置为根据第一加法器的进位是否产生预置值或0值; 以及第二加法器，其被配置为接收第一加法器的输出信号和预设单元的输出信号以执行加法运算，并将加法运算输入到寄存器和包括累加器的数据加权平均装置，可以提高 通过生成除了2n个DAC代码之外的多个DAC代码，在数据转换器中发生非线性。

    Subsampling receiver using interstage off-chip RF band pass filter
    10.
    发明授权
    Subsampling receiver using interstage off-chip RF band pass filter 有权
    子采样接收机采用片间片外RF带通滤波器

    公开(公告)号：US09209844B2

    公开(公告)日：2015-12-08

    申请号：US13737726

    申请日：2013-01-09

    申请人： Electronics and Telecommunications Research Institute

    发明人： Seon-Ho Han ,  Hyun Kyu Yu

    IPC分类号： H04B1/10 ,  H04B1/22 ,  H04B1/06 ,  H04B1/00

    CPC分类号： H04B1/06 ,  H04B1/0014

    摘要： The inventive concept relates to a wireless communication receiver. The wireless communication receiver includes a second off-chip RF filter, an RF-to-digital converter and a digital pre-processor processing a signal converted into a digital. The RF-to-digital converter converts an RF signal being received into a digital signal of DC frequency band or intermediate frequency band and has a dynamic range that can process a wanted RF band signal and unwanted signals near to the wanted RF band signal. The digital pre-processor digitally controls a signal gain to transmit it to a modulator/demodulator.

    摘要翻译： 本发明构思涉及无线通信接收机。 无线通信接收机包括第二片外RF滤波器，RF到数字转换器和处理转换成数字信号的数字预处理器。 RF-数字转换器将接收的RF信号转换为DC频带或中频带的数字信号，并且具有可处理所需RF频带信号的动态范围和靠近所需RF频带信号的不需要的信号。 数字预处理器以数字方式控制信号增益，将其发送到调制器/解调器。