公开(公告)号：US20140235016A1

公开(公告)日：2014-08-21

申请号：US14155243

申请日：2014-01-14

Applicant: SIGETRONICS Inc. ,  Electronics and Telecommunications Research Institute

Inventor： Jong-Moon PARK ,  Jin Ho LEE ,  Deok-Ho CHO ,  Kyu-Hwan SHIM

IPC: H01L23/00

CPC classification number: H01L23/4827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/04026 ,  H01L2224/05138 ,  H01L2224/05638 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/2745 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29144 ,  H01L2224/29166 ,  H01L2224/29171 ,  H01L2224/32227 ,  H01L2224/32502 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83805 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/01026 ,  H01L2924/01014 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor package, including preparing a die including a first metal layer and a second metal layer which are sequentially stacked on a silicon substrate, preparing a package substrate including a lead frame, and forming an adhesive layer between the lead frame and the first metal layer and attaching the die to the package substrate, wherein the forming of the adhesive layer is performed by eutectic bonding between the silicon substrate and the second metal layer. According to the semiconductor package according to an embodiment of the present invention, an adhesive layer can be easily formed by eutectic bonding without a process of forming a preform.

Abstract translation: 提供一种制造半导体封装的方法，包括制备包括依次层叠在硅衬底上的第一金属层和第二金属层的管芯，制备包括引线框架的封装衬底，以及在引线之间形成粘合剂层 框架和第一金属层并将管芯附接到封装衬底，其中通过硅衬底和第二金属层之间的共晶接合来执行粘合剂层的形成。 根据本发明的实施方式的半导体封装，通过共晶接合可以容易地形成粘合层，而不需要形成预成型体。

公开(公告)号：US20150283743A1

公开(公告)日：2015-10-08

申请号：US14517482

申请日：2014-10-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jong-Moon PARK ,  Kunsik PARK ,  Dong Suk JUN ,  Seong Wook YOO ,  Sang Gi KIM ,  Jin Ho LEE

IPC: B29C45/17

CPC classification number: B29C33/3842 ,  B29C45/17 ,  B29C59/002 ,  B29C2033/385 ,  B29L2031/757

Abstract: Provided is a method of fabricating a mold, the method including: forming a first preliminary layer and a second preliminary layer, which are spaced apart from each other and stacked on a substrate; forming a first pattern by patterning the first preliminary layer; forming a first spacer on both sidewalls of the first pattern;forming a second pattern by etching the second preliminary layer by using the first spacer as an etching mask; forming a multilayer structure including the first pattern and the second pattern on the substrate by removing the first spacer; and forming a mold layer covering the multilayer structure.

Abstract translation: 提供一种制造模具的方法，该方法包括：形成彼此间隔开并堆叠在基板上的第一预备层和第二预备层; 通过图案化第一预备层形成第一图案; 在所述第一图案的两个侧壁上形成第一间隔物; 通过使用第一间隔件作为蚀刻掩模蚀刻第二预备层来形成第二图案; 通过去除所述第一间隔件在所述基板上形成包括所述第一图案和所述第二图案的多层结构; 以及形成覆盖所述多层结构的模具层。

公开(公告)号：US20140091388A1

公开(公告)日：2014-04-03

申请号：US14100780

申请日：2013-12-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Gi KIM ,  Jin-Gun KOO ,  Seong Wook YOO ,  Jong-Moon PARK ,  Jin Ho LEE ,  KYOUNG IL NA ,  Yil Suk Yang ,  Jongdae KIM

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。