公开(公告)号：US20140077302A1

公开(公告)日：2014-03-20

申请号：US13846701

申请日：2013-03-18

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kunsik PARK ,  KYOUNG IL NA ,  Jin Ho LEE ,  JIN-GUN KOO

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/0619 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/6609 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/861

Abstract: According to a power rectifying device of embodiments of the inventive concept, a gate electrode, a source region, and a body region are connected in common to a first terminal, and a substrate beside the body region is connected to a second terminal. Thus, the power rectifying device having two terminals is realized. The gate electrode has s spacer-shape. Thus, a width of the gate electrode may be controlled to accurately control a channel length of a channel region of a transistor structure in the power rectifying device.

Abstract translation: 根据本发明构思的实施例的功率整流装置，栅电极，源极区和体区共同连接到第一端子，并且身体区域旁边的衬底连接到第二端子。 因此，实现具有两个端子的动力整流装置。 栅电极具有间隔物形状。 因此，可以控制栅电极的宽度以精确地控制功率整流装置中的晶体管结构的沟道区的沟道长度。

公开(公告)号：US20150283743A1

公开(公告)日：2015-10-08

申请号：US14517482

申请日：2014-10-17

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jong-Moon PARK ,  Kunsik PARK ,  Dong Suk JUN ,  Seong Wook YOO ,  Sang Gi KIM ,  Jin Ho LEE

IPC: B29C45/17

CPC classification number: B29C33/3842 ,  B29C45/17 ,  B29C59/002 ,  B29C2033/385 ,  B29L2031/757

Abstract: Provided is a method of fabricating a mold, the method including: forming a first preliminary layer and a second preliminary layer, which are spaced apart from each other and stacked on a substrate; forming a first pattern by patterning the first preliminary layer; forming a first spacer on both sidewalls of the first pattern;forming a second pattern by etching the second preliminary layer by using the first spacer as an etching mask; forming a multilayer structure including the first pattern and the second pattern on the substrate by removing the first spacer; and forming a mold layer covering the multilayer structure.

Abstract translation: 提供一种制造模具的方法，该方法包括：形成彼此间隔开并堆叠在基板上的第一预备层和第二预备层; 通过图案化第一预备层形成第一图案; 在所述第一图案的两个侧壁上形成第一间隔物; 通过使用第一间隔件作为蚀刻掩模蚀刻第二预备层来形成第二图案; 通过去除所述第一间隔件在所述基板上形成包括所述第一图案和所述第二图案的多层结构; 以及形成覆盖所述多层结构的模具层。

公开(公告)号：US20140197449A1

公开(公告)日：2014-07-17

申请号：US14155232

申请日：2014-01-14

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kunsik PARK ,  Kyoung IL NA ,  JIN-GUN KOO ,  Jin Ho LEE ,  Jong II WON

IPC: H01L29/747

CPC classification number: H01L29/861 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238

Abstract: Provided is a semiconductor rectifier device. The semiconductor rectifier device may include a substrate doped with a first conductive type, a second electrode provided on a bottom surface of the substrate, an active region and a field region defined on the substrate, a gate provided in the active region, a gate insulating film provided between the gate and the substrate, body regions provided on the substrate adjacent to first and second sides of the gate, facing each other, and doped with a second conductive type dopant different from the first conductive type, and a second conductive type plug region formed on the substrate adjacent to third and fourth sides of the gate, connecting the first and second sides.

Abstract translation: 提供了一种半导体整流器件。 半导体整流器件可以包括掺杂有第一导电类型的衬底，设置在衬底的底表面上的第二电极，在衬底上限定的有源区和场区，设置在有源区中的栅极，栅极绝缘 提供在所述栅极和所述基板之间的薄膜，设置在所述基板上的与所述栅极的第一和第二侧相邻的主体区域，彼此面对，并且掺杂有不同于所述第一导电类型的第二导电型掺杂物;以及第二导电型插塞 区域，形成在与栅极的第三和第四侧相邻的衬底上，连接第一和第二面。