Capsule endoscope image receiver and capsule endoscope device having the same

    公开(公告)号:US11478137B2

    公开(公告)日:2022-10-25

    申请号:US16842497

    申请日:2020-04-07

    Abstract: A capsule endoscope image receiver includes a receiving electrode unit that receives first and second differential signals from a capsule endoscope image transmitter through a human body communication channel, an analog amplifying unit that receives the first and second differential signals and outputs first and second amplified differential signals, and a signal restoring unit that receives the first and second amplified differential signals and restores image information. The analog amplifying unit includes a first amplifier that outputs the first amplified differential signal, a second amplifier that outputs the second amplified differential signal, and an input impedance that is connected between a first inverting input terminal of the first amplifier and a second inverting input terminal of the second amplifier and obtains a gain of differential signal amplification in which a high frequency component of the first and second amplified differential signals is greater than a low frequency component.

    Human body communication device having single electrode

    公开(公告)号:US11233583B2

    公开(公告)日:2022-01-25

    申请号:US17020400

    申请日:2020-09-14

    Abstract: A human body communication device includes an electrode, a matching circuit, a switch providing a first path electrically connected to the matching circuit and a second path electrically connected to the matching circuit, a sensor, in a first state, connected to the matching circuit through the switch, outputting a first sensing signal to the matching circuit, and outputting a second sensing signal when a difference between a signal generated from the matching circuit in response to the first sensing signal and the first sensing signal is greater than or equal to a threshold, a transmitter, in a second state, connected to the matching circuit through the switch, and outputting a data signal to the matching circuit, and a controller controlling the switch from the first state to the second state in response to receiving the second sensing signal from the sensor, in the first state.

    SPIKE NEURAL NETWORK CIRCUIT AND OPERATION METHOD THEREOF

    公开(公告)号:US20240378411A1

    公开(公告)日:2024-11-14

    申请号:US18421055

    申请日:2024-01-24

    Abstract: Disclosed is a spike neural network circuit, which includes an axon generating a spike input, a synapse performing a weight calculation and generating a membrane signal based on the weight calculation, and a neuron accumulating the membrane signal to generate a spike output, and the neuron includes a firing unit that compares a potential of a membrane node where the membrane signal is accumulated with a reference potential and fires based on the comparison result, membrane capacitors connected to the membrane node, a switch controller that outputs switching signals based on the firing of the firing unit, switches that connects each of membrane capacitors to one of a power supply voltage and a ground voltage in response to the switching signals, and a spike output generator that generates the spike output based on the plurality of switching signals and the firing of the firing unit.

    Low power system on chip
    10.
    发明授权

    公开(公告)号:US12147263B2

    公开(公告)日:2024-11-19

    申请号:US17847636

    申请日:2022-06-23

    Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.

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